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linux
clk: qcom: tcsrcc-glymur: Update register offsets for clock refs
Update the register offsets for all the clock ref branches to match the
new address mapping in the TCSR subsystem.
Fixes: 2c1d6ce4f3da ("clk: qcom: Add TCSR clock driver for Glymur SoC")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Tested-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251031-tcsrcc_glymur-v1-1-0efb031f0ac5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Taniya Das
and committed by
Bjorn Andersson
a4aa1ceb
0820c937
+27
-27
+27
-27
drivers/clk/qcom/tcsrcc-glymur.c
+27
-27
drivers/clk/qcom/tcsrcc-glymur.c
···
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};
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static struct clk_branch tcsr_edp_clkref_en = {
31
-
.halt_reg = 0x1c,
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+
.halt_reg = 0x60,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x1c,
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+
.enable_reg = 0x60,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_edp_clkref_en",
···
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};
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static struct clk_branch tcsr_pcie_1_clkref_en = {
48
-
.halt_reg = 0x4,
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+
.halt_reg = 0x48,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x4,
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+
.enable_reg = 0x48,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_pcie_1_clkref_en",
···
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};
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static struct clk_branch tcsr_pcie_2_clkref_en = {
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-
.halt_reg = 0x8,
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+
.halt_reg = 0x4c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x8,
68
+
.enable_reg = 0x4c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_pcie_2_clkref_en",
···
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};
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static struct clk_branch tcsr_pcie_3_clkref_en = {
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-
.halt_reg = 0x10,
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+
.halt_reg = 0x54,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x10,
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+
.enable_reg = 0x54,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_pcie_3_clkref_en",
···
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};
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static struct clk_branch tcsr_pcie_4_clkref_en = {
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-
.halt_reg = 0x14,
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+
.halt_reg = 0x58,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x14,
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+
.enable_reg = 0x58,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_pcie_4_clkref_en",
···
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};
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static struct clk_branch tcsr_usb2_1_clkref_en = {
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-
.halt_reg = 0x28,
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+
.halt_reg = 0x6c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x28,
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+
.enable_reg = 0x6c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb2_1_clkref_en",
···
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};
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static struct clk_branch tcsr_usb2_2_clkref_en = {
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-
.halt_reg = 0x2c,
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+
.halt_reg = 0x70,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x2c,
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+
.enable_reg = 0x70,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb2_2_clkref_en",
···
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};
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static struct clk_branch tcsr_usb2_3_clkref_en = {
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-
.halt_reg = 0x30,
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+
.halt_reg = 0x74,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x30,
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+
.enable_reg = 0x74,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb2_3_clkref_en",
···
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};
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static struct clk_branch tcsr_usb2_4_clkref_en = {
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-
.halt_reg = 0x44,
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+
.halt_reg = 0x88,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x44,
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+
.enable_reg = 0x88,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb2_4_clkref_en",
···
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};
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static struct clk_branch tcsr_usb3_0_clkref_en = {
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-
.halt_reg = 0x20,
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+
.halt_reg = 0x64,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x20,
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+
.enable_reg = 0x64,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb3_0_clkref_en",
···
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};
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static struct clk_branch tcsr_usb3_1_clkref_en = {
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-
.halt_reg = 0x24,
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+
.halt_reg = 0x68,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x24,
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+
.enable_reg = 0x68,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb3_1_clkref_en",
···
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};
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static struct clk_branch tcsr_usb4_1_clkref_en = {
218
-
.halt_reg = 0x0,
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+
.halt_reg = 0x44,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x0,
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+
.enable_reg = 0x44,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb4_1_clkref_en",
···
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};
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static struct clk_branch tcsr_usb4_2_clkref_en = {
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-
.halt_reg = 0x18,
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+
.halt_reg = 0x5c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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-
.enable_reg = 0x18,
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+
.enable_reg = 0x5c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb4_2_clkref_en",
···
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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-
.max_register = 0x44,
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+
.max_register = 0x94,
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.fast_io = true,
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};
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