tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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os
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Merge branch '20221213152617.296426-1-konrad.dybcio@linaro.org' into HEAD
Merge DT binding to gain Camera clock defines for SM6350
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Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml
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Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm6350-camcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Camera Clock & Reset Controller on SM6350
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maintainers:
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- Konrad Dybcio <konrad.dybcio@linaro.org>
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description: |
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Qualcomm camera clock control module provides the clocks, resets and power
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domains on SM6350.
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See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h
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properties:
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compatible:
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const: qcom,sm6350-camcc
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clocks:
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items:
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- description: Board XO source
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@ad00000 {
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compatible = "qcom,sm6350-camcc";
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reg = <0x0ad00000 0x16000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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include/dt-bindings/clock/qcom,sm6350-camcc.h
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include/dt-bindings/clock/qcom,sm6350-camcc.h
···
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Linaro Limited
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_CAMCC_SM6350_H
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#define _DT_BINDINGS_CLK_QCOM_CAMCC_SM6350_H
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/* CAMCC clocks */
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#define CAMCC_PLL2_OUT_EARLY 0
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#define CAMCC_PLL0 1
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#define CAMCC_PLL0_OUT_EVEN 2
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#define CAMCC_PLL1 3
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#define CAMCC_PLL1_OUT_EVEN 4
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#define CAMCC_PLL2 5
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#define CAMCC_PLL2_OUT_MAIN 6
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#define CAMCC_PLL3 7
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#define CAMCC_BPS_AHB_CLK 8
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#define CAMCC_BPS_AREG_CLK 9
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#define CAMCC_BPS_AXI_CLK 10
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#define CAMCC_BPS_CLK 11
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#define CAMCC_BPS_CLK_SRC 12
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#define CAMCC_CAMNOC_ATB_CLK 13
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#define CAMCC_CAMNOC_AXI_CLK 14
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#define CAMCC_CCI_0_CLK 15
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#define CAMCC_CCI_0_CLK_SRC 16
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#define CAMCC_CCI_1_CLK 17
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#define CAMCC_CCI_1_CLK_SRC 18
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#define CAMCC_CORE_AHB_CLK 19
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#define CAMCC_CPAS_AHB_CLK 20
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#define CAMCC_CPHY_RX_CLK_SRC 21
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#define CAMCC_CSI0PHYTIMER_CLK 22
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#define CAMCC_CSI0PHYTIMER_CLK_SRC 23
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#define CAMCC_CSI1PHYTIMER_CLK 24
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#define CAMCC_CSI1PHYTIMER_CLK_SRC 25
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#define CAMCC_CSI2PHYTIMER_CLK 26
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#define CAMCC_CSI2PHYTIMER_CLK_SRC 27
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#define CAMCC_CSI3PHYTIMER_CLK 28
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#define CAMCC_CSI3PHYTIMER_CLK_SRC 29
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#define CAMCC_CSIPHY0_CLK 30
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#define CAMCC_CSIPHY1_CLK 31
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#define CAMCC_CSIPHY2_CLK 32
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#define CAMCC_CSIPHY3_CLK 33
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#define CAMCC_FAST_AHB_CLK_SRC 34
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#define CAMCC_ICP_APB_CLK 35
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#define CAMCC_ICP_ATB_CLK 36
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#define CAMCC_ICP_CLK 37
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#define CAMCC_ICP_CLK_SRC 38
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#define CAMCC_ICP_CTI_CLK 39
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#define CAMCC_ICP_TS_CLK 40
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#define CAMCC_IFE_0_AXI_CLK 41
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#define CAMCC_IFE_0_CLK 42
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#define CAMCC_IFE_0_CLK_SRC 43
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#define CAMCC_IFE_0_CPHY_RX_CLK 44
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#define CAMCC_IFE_0_CSID_CLK 45
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#define CAMCC_IFE_0_CSID_CLK_SRC 46
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#define CAMCC_IFE_0_DSP_CLK 47
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#define CAMCC_IFE_1_AXI_CLK 48
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#define CAMCC_IFE_1_CLK 49
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#define CAMCC_IFE_1_CLK_SRC 50
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#define CAMCC_IFE_1_CPHY_RX_CLK 51
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#define CAMCC_IFE_1_CSID_CLK 52
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#define CAMCC_IFE_1_CSID_CLK_SRC 53
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#define CAMCC_IFE_1_DSP_CLK 54
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#define CAMCC_IFE_2_AXI_CLK 55
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#define CAMCC_IFE_2_CLK 56
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#define CAMCC_IFE_2_CLK_SRC 57
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#define CAMCC_IFE_2_CPHY_RX_CLK 58
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#define CAMCC_IFE_2_CSID_CLK 59
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#define CAMCC_IFE_2_CSID_CLK_SRC 60
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#define CAMCC_IFE_2_DSP_CLK 61
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#define CAMCC_IFE_LITE_CLK 62
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#define CAMCC_IFE_LITE_CLK_SRC 63
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#define CAMCC_IFE_LITE_CPHY_RX_CLK 64
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#define CAMCC_IFE_LITE_CSID_CLK 65
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#define CAMCC_IFE_LITE_CSID_CLK_SRC 66
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#define CAMCC_IPE_0_AHB_CLK 67
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#define CAMCC_IPE_0_AREG_CLK 68
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#define CAMCC_IPE_0_AXI_CLK 69
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#define CAMCC_IPE_0_CLK 70
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#define CAMCC_IPE_0_CLK_SRC 71
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#define CAMCC_JPEG_CLK 72
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#define CAMCC_JPEG_CLK_SRC 73
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#define CAMCC_LRME_CLK 74
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#define CAMCC_LRME_CLK_SRC 75
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#define CAMCC_MCLK0_CLK 76
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#define CAMCC_MCLK0_CLK_SRC 77
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#define CAMCC_MCLK1_CLK 78
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#define CAMCC_MCLK1_CLK_SRC 79
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#define CAMCC_MCLK2_CLK 80
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#define CAMCC_MCLK2_CLK_SRC 81
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#define CAMCC_MCLK3_CLK 82
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#define CAMCC_MCLK3_CLK_SRC 83
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#define CAMCC_MCLK4_CLK 84
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#define CAMCC_MCLK4_CLK_SRC 85
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#define CAMCC_SLOW_AHB_CLK_SRC 86
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#define CAMCC_SOC_AHB_CLK 87
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#define CAMCC_SYS_TMR_CLK 88
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/* GDSCs */
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#define BPS_GDSC 0
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#define IPE_0_GDSC 1
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#define IFE_0_GDSC 2
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#define IFE_1_GDSC 3
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#define IFE_2_GDSC 4
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#define TITAN_TOP_GDSC 5
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#endif