drm/amdgpu: drop nv_set_ip_blocks() · tjh.dev/kernel@bf99b9b

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

drm/amdgpu: drop nv_set_ip_blocks()

No longer used since IP enumeration is now driven by
amdgpu IP discovery code.

Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 4 years ago bf99b9b0 7092432e

-294

2 changed files

expand all

drivers

gpu

drm

amd

amdgpu

nv.c

nv.h

-293

drivers/gpu/drm/amd/amdgpu/nv.c

··· 607 607 .funcs = &nv_common_ip_funcs, 608 608 }; 609 609 610 - static int nv_reg_base_init(struct amdgpu_device *adev) 611 - { 612 - int r; 613 - 614 - if (amdgpu_discovery) { 615 - r = amdgpu_discovery_reg_base_init(adev); 616 - if (r) { 617 - DRM_WARN("failed to init reg base from ip discovery table, " 618 - "fallback to legacy init method\n"); 619 - goto legacy_init; 620 - } 621 - 622 - amdgpu_discovery_harvest_ip(adev); 623 - 624 - return 0; 625 - } 626 - 627 - legacy_init: 628 - switch (adev->asic_type) { 629 - case CHIP_NAVI10: 630 - navi10_reg_base_init(adev); 631 - break; 632 - case CHIP_NAVI14: 633 - navi14_reg_base_init(adev); 634 - break; 635 - case CHIP_NAVI12: 636 - navi12_reg_base_init(adev); 637 - break; 638 - case CHIP_SIENNA_CICHLID: 639 - case CHIP_NAVY_FLOUNDER: 640 - sienna_cichlid_reg_base_init(adev); 641 - break; 642 - case CHIP_VANGOGH: 643 - vangogh_reg_base_init(adev); 644 - break; 645 - case CHIP_DIMGREY_CAVEFISH: 646 - dimgrey_cavefish_reg_base_init(adev); 647 - break; 648 - case CHIP_BEIGE_GOBY: 649 - beige_goby_reg_base_init(adev); 650 - break; 651 - case CHIP_YELLOW_CARP: 652 - yellow_carp_reg_base_init(adev); 653 - break; 654 - case CHIP_CYAN_SKILLFISH: 655 - cyan_skillfish_reg_base_init(adev); 656 - break; 657 - default: 658 - return -EINVAL; 659 - } 660 - 661 - return 0; 662 - } 663 - 664 610 void nv_set_virt_ops(struct amdgpu_device *adev) 665 611 { 666 612 adev->virt.ops = &xgpu_nv_virt_ops; 667 - } 668 - 669 - int nv_set_ip_blocks(struct amdgpu_device *adev) 670 - { 671 - int r; 672 - 673 - if (adev->asic_type == CHIP_CYAN_SKILLFISH) { 674 - adev->nbio.funcs = &nbio_v2_3_funcs; 675 - adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 676 - } else if (adev->flags & AMD_IS_APU) { 677 - adev->nbio.funcs = &nbio_v7_2_funcs; 678 - adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 679 - } else { 680 - adev->nbio.funcs = &nbio_v2_3_funcs; 681 - adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 682 - } 683 - adev->hdp.funcs = &hdp_v5_0_funcs; 684 - 685 - if (adev->asic_type >= CHIP_SIENNA_CICHLID) 686 - adev->smuio.funcs = &smuio_v11_0_6_funcs; 687 - else 688 - adev->smuio.funcs = &smuio_v11_0_funcs; 689 - 690 - if (adev->asic_type == CHIP_SIENNA_CICHLID) 691 - adev->gmc.xgmi.supported = true; 692 - 693 - /* Set IP register base before any HW register access */ 694 - r = nv_reg_base_init(adev); 695 - if (r) 696 - return r; 697 - 698 - switch (adev->asic_type) { 699 - case CHIP_NAVI10: 700 - case CHIP_NAVI14: 701 - amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 702 - amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 703 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 704 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 705 - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 706 - !amdgpu_sriov_vf(adev)) 707 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 708 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 709 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 710 - #if defined(CONFIG_DRM_AMD_DC) 711 - else if (amdgpu_device_has_dc_support(adev)) 712 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 713 - #endif 714 - amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 715 - amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 716 - if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 717 - !amdgpu_sriov_vf(adev)) 718 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 719 - amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 720 - amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 721 - if (adev->enable_mes) 722 - amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 723 - break; 724 - case CHIP_NAVI12: 725 - amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 726 - amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 727 - if (!amdgpu_sriov_vf(adev)) { 728 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 729 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 730 - } else { 731 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 732 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 733 - } 734 - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 735 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 736 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 737 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 738 - #if defined(CONFIG_DRM_AMD_DC) 739 - else if (amdgpu_device_has_dc_support(adev)) 740 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 741 - #endif 742 - amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 743 - amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 744 - if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 745 - !amdgpu_sriov_vf(adev)) 746 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 747 - amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 748 - if (!amdgpu_sriov_vf(adev)) 749 - amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 750 - break; 751 - case CHIP_SIENNA_CICHLID: 752 - amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 753 - amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 754 - if (!amdgpu_sriov_vf(adev)) { 755 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 756 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 757 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 758 - } else { 759 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 760 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 761 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 762 - } 763 - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 764 - is_support_sw_smu(adev)) 765 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 766 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 767 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 768 - #if defined(CONFIG_DRM_AMD_DC) 769 - else if (amdgpu_device_has_dc_support(adev)) 770 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 771 - #endif 772 - amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 773 - amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 774 - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 775 - if (!amdgpu_sriov_vf(adev)) 776 - amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 777 - if (adev->enable_mes) 778 - amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 779 - break; 780 - case CHIP_NAVY_FLOUNDER: 781 - amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 782 - amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 783 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 784 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 785 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 786 - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 787 - is_support_sw_smu(adev)) 788 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 789 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 790 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 791 - #if defined(CONFIG_DRM_AMD_DC) 792 - else if (amdgpu_device_has_dc_support(adev)) 793 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 794 - #endif 795 - amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 796 - amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 797 - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 798 - amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 799 - if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 800 - is_support_sw_smu(adev)) 801 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 802 - break; 803 - case CHIP_VANGOGH: 804 - amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 805 - amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 806 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 807 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 808 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 809 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 810 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 811 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 812 - #if defined(CONFIG_DRM_AMD_DC) 813 - else if (amdgpu_device_has_dc_support(adev)) 814 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 815 - #endif 816 - amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 817 - amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 818 - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 819 - amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 820 - break; 821 - case CHIP_DIMGREY_CAVEFISH: 822 - amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 823 - amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 824 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 825 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 826 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 827 - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 828 - is_support_sw_smu(adev)) 829 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 830 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 831 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 832 - #if defined(CONFIG_DRM_AMD_DC) 833 - else if (amdgpu_device_has_dc_support(adev)) 834 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 835 - #endif 836 - amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 837 - amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 838 - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 839 - amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 840 - break; 841 - case CHIP_BEIGE_GOBY: 842 - amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 843 - amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 844 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 845 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 846 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 847 - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 848 - is_support_sw_smu(adev)) 849 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 850 - amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 851 - amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 852 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 853 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 854 - #if defined(CONFIG_DRM_AMD_DC) 855 - else if (amdgpu_device_has_dc_support(adev)) 856 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 857 - #endif 858 - if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 859 - is_support_sw_smu(adev)) 860 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 861 - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 862 - break; 863 - case CHIP_YELLOW_CARP: 864 - amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 865 - amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 866 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 867 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 868 - amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 869 - amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 870 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 871 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 872 - amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 873 - amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 874 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 875 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 876 - #if defined(CONFIG_DRM_AMD_DC) 877 - else if (amdgpu_device_has_dc_support(adev)) 878 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 879 - #endif 880 - amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 881 - amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 882 - break; 883 - case CHIP_CYAN_SKILLFISH: 884 - amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 885 - amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 886 - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 887 - if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 888 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 889 - amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 890 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 891 - } 892 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 893 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 894 - #if defined(CONFIG_DRM_AMD_DC) 895 - else if (amdgpu_device_has_dc_support(adev)) 896 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 897 - #endif 898 - amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 899 - amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 900 - break; 901 - default: 902 - return -EINVAL; 903 - } 904 - 905 - return 0; 906 613 } 907 614 908 615 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)

-1

drivers/gpu/drm/amd/amdgpu/nv.h

··· 31 31 void nv_grbm_select(struct amdgpu_device *adev, 32 32 u32 me, u32 pipe, u32 queue, u32 vmid); 33 33 void nv_set_virt_ops(struct amdgpu_device *adev); 34 - int nv_set_ip_blocks(struct amdgpu_device *adev); 35 34 int navi10_reg_base_init(struct amdgpu_device *adev); 36 35 int navi14_reg_base_init(struct amdgpu_device *adev); 37 36 int navi12_reg_base_init(struct amdgpu_device *adev);