tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: drop soc15_set_ip_blocks()

No longer used since IP enumeration is now driven by
amdgpu IP discovery code.

Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 7092432e 0f3d2b68

-180
-179
drivers/gpu/drm/amd/amdgpu/soc15.c
··· 780 780 soc15_reg_base_init(adev); 781 781 } 782 782 783 - int soc15_set_ip_blocks(struct amdgpu_device *adev) 784 - { 785 - /* for bare metal case */ 786 - if (!amdgpu_sriov_vf(adev)) 787 - soc15_reg_base_init(adev); 788 - 789 - if (adev->flags & AMD_IS_APU) { 790 - adev->nbio.funcs = &nbio_v7_0_funcs; 791 - adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 792 - } else if (adev->asic_type == CHIP_VEGA20 || 793 - adev->asic_type == CHIP_ARCTURUS || 794 - adev->asic_type == CHIP_ALDEBARAN) { 795 - adev->nbio.funcs = &nbio_v7_4_funcs; 796 - adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 797 - } else { 798 - adev->nbio.funcs = &nbio_v6_1_funcs; 799 - adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 800 - } 801 - adev->hdp.funcs = &hdp_v4_0_funcs; 802 - 803 - if (adev->asic_type == CHIP_VEGA20 || 804 - adev->asic_type == CHIP_ARCTURUS || 805 - adev->asic_type == CHIP_ALDEBARAN) 806 - adev->df.funcs = &df_v3_6_funcs; 807 - else 808 - adev->df.funcs = &df_v1_7_funcs; 809 - 810 - if (adev->asic_type == CHIP_VEGA20 || 811 - adev->asic_type == CHIP_ARCTURUS) 812 - adev->smuio.funcs = &smuio_v11_0_funcs; 813 - else if (adev->asic_type == CHIP_ALDEBARAN) 814 - adev->smuio.funcs = &smuio_v13_0_funcs; 815 - else 816 - adev->smuio.funcs = &smuio_v9_0_funcs; 817 - 818 - adev->rev_id = soc15_get_rev_id(adev); 819 - 820 - switch (adev->asic_type) { 821 - case CHIP_VEGA10: 822 - case CHIP_VEGA12: 823 - case CHIP_VEGA20: 824 - amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 825 - amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 826 - 827 - /* For Vega10 SR-IOV, PSP need to be initialized before IH */ 828 - if (amdgpu_sriov_vf(adev)) { 829 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 830 - if (adev->asic_type == CHIP_VEGA20) 831 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 832 - else 833 - amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 834 - } 835 - if (adev->asic_type == CHIP_VEGA20) 836 - amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 837 - else 838 - amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 839 - } else { 840 - if (adev->asic_type == CHIP_VEGA20) 841 - amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 842 - else 843 - amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 844 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 845 - if (adev->asic_type == CHIP_VEGA20) 846 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 847 - else 848 - amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 849 - } 850 - } 851 - amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 852 - amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 853 - if (is_support_sw_smu(adev)) { 854 - if (!amdgpu_sriov_vf(adev)) 855 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 856 - } else { 857 - amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 858 - } 859 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 860 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 861 - #if defined(CONFIG_DRM_AMD_DC) 862 - else if (amdgpu_device_has_dc_support(adev)) 863 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 864 - #endif 865 - if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 866 - amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 867 - amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 868 - } 869 - break; 870 - case CHIP_RAVEN: 871 - amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 872 - amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 873 - amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 874 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 875 - amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 876 - amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 877 - amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 878 - amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 879 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 880 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 881 - #if defined(CONFIG_DRM_AMD_DC) 882 - else if (amdgpu_device_has_dc_support(adev)) 883 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 884 - #endif 885 - amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 886 - break; 887 - case CHIP_ARCTURUS: 888 - amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 889 - amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 890 - 891 - if (amdgpu_sriov_vf(adev)) { 892 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 893 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 894 - amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 895 - } else { 896 - amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 897 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 898 - amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 899 - } 900 - 901 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 902 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 903 - amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 904 - amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 905 - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 906 - 907 - if (amdgpu_sriov_vf(adev)) { 908 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 909 - amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 910 - } else { 911 - amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 912 - } 913 - if (!amdgpu_sriov_vf(adev)) 914 - amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 915 - break; 916 - case CHIP_RENOIR: 917 - amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 918 - amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 919 - amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 920 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 921 - amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 922 - amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 923 - amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 924 - amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 925 - if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 926 - amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 927 - #if defined(CONFIG_DRM_AMD_DC) 928 - else if (amdgpu_device_has_dc_support(adev)) 929 - amdgpu_device_ip_block_add(adev, &dm_ip_block); 930 - #endif 931 - amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 932 - amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 933 - break; 934 - case CHIP_ALDEBARAN: 935 - amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 936 - amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 937 - 938 - if (amdgpu_sriov_vf(adev)) { 939 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 940 - amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 941 - amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 942 - } else { 943 - amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 944 - if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 945 - amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 946 - } 947 - 948 - amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 949 - amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 950 - 951 - amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 952 - amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 953 - amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 954 - break; 955 - default: 956 - return -EINVAL; 957 - } 958 - 959 - return 0; 960 - } 961 - 962 783 static bool soc15_need_full_reset(struct amdgpu_device *adev) 963 784 { 964 785 /* change this when we implement soft reset */
-1
drivers/gpu/drm/amd/amdgpu/soc15.h
··· 102 102 void soc15_grbm_select(struct amdgpu_device *adev, 103 103 u32 me, u32 pipe, u32 queue, u32 vmid); 104 104 void soc15_set_virt_ops(struct amdgpu_device *adev); 105 - int soc15_set_ip_blocks(struct amdgpu_device *adev); 106 105 107 106 void soc15_program_register_sequence(struct amdgpu_device *adev, 108 107 const struct soc15_reg_golden *registers,