tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY

The PCIe PHY version used in SDX55 is v4.20 which has different register
offsets compared to the v4.0x PHYs. So separate register defines are
used for init sequence and PHY status.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210427065400.18958-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Manivannan Sadhasivam and committed by
Vinod Koul be0ddb5d 952b702b

+187 -1
+131
drivers/phy/qualcomm/phy-qcom-qmp.c
··· 35 35 #define PLL_READY_GATE_EN BIT(3) 36 36 /* QPHY_PCS_STATUS bit */ 37 37 #define PHYSTATUS BIT(6) 38 + #define PHYSTATUS_4_20 BIT(7) 38 39 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ 39 40 #define PCS_READY BIT(0) 40 41 ··· 2225 2224 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 2226 2225 }; 2227 2226 2227 + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 2228 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 2229 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 2230 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 2231 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 2232 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 2233 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 2234 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 2235 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 2236 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 2237 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 2238 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 2239 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 2240 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 2241 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 2242 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 2243 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 2244 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 2245 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 2246 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 2247 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 2248 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2249 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2250 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2251 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2252 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 2253 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 2254 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2255 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 2256 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 2257 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 2258 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 2259 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), 2260 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 2261 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 2262 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 2263 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 2264 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 2265 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 2266 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 2267 + }; 2268 + 2269 + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 2270 + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 2271 + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 2272 + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 2273 + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 2274 + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 2275 + }; 2276 + 2277 + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 2278 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 2279 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 2280 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 2281 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 2282 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 2283 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 2284 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 2285 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 2286 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 2287 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 2288 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 2289 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 2290 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 2291 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 2292 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 2293 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 2294 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 2295 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 2296 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 2297 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 2298 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 2299 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 2300 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 2301 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2302 + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 2303 + }; 2304 + 2305 + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 2306 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 2307 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 2308 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 2309 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 2310 + }; 2311 + 2312 + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 2313 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 2314 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 2315 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 2316 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 2317 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2318 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 2319 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 2320 + }; 2321 + 2228 2322 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { 2229 2323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), 2230 2324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), ··· 3556 3460 .has_pwrdn_delay = true, 3557 3461 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 3558 3462 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 3463 + }; 3464 + 3465 + static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 3466 + .type = PHY_TYPE_PCIE, 3467 + .nlanes = 2, 3468 + 3469 + .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, 3470 + .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 3471 + .tx_tbl = sdx55_qmp_pcie_tx_tbl, 3472 + .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 3473 + .rx_tbl = sdx55_qmp_pcie_rx_tbl, 3474 + .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 3475 + .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, 3476 + .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 3477 + .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, 3478 + .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 3479 + .clk_list = sdm845_pciephy_clk_l, 3480 + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 3481 + .reset_list = sdm845_pciephy_reset_l, 3482 + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3483 + .vreg_list = qmp_phy_vreg_l, 3484 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3485 + .regs = sm8250_pcie_regs_layout, 3486 + 3487 + .start_ctrl = PCS_START | SERDES_START, 3488 + .pwrdn_ctrl = SW_PWRDN, 3489 + .phy_status = PHYSTATUS_4_20, 3490 + 3491 + .is_dual_lane_phy = true, 3492 + .has_pwrdn_delay = true, 3493 + .pwrdn_delay_min = 995, /* us */ 3494 + .pwrdn_delay_max = 1005, /* us */ 3559 3495 }; 3560 3496 3561 3497 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { ··· 5292 5164 }, { 5293 5165 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 5294 5166 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 5167 + }, { 5168 + .compatible = "qcom,sdx55-qmp-pcie-phy", 5169 + .data = &sdx55_qmp_pciephy_cfg, 5295 5170 }, { 5296 5171 .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 5297 5172 .data = &sdx55_usb3_uniphy_cfg,
+56 -1
drivers/phy/qualcomm/phy-qcom-qmp.h
··· 552 552 #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 553 553 #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 554 554 #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 555 + #define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 555 556 #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 556 557 #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 557 558 #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 ··· 567 566 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 568 567 #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 569 568 #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 569 + #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 570 + #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 570 571 #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 571 572 #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 572 573 #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 ··· 586 583 #define QSERDES_V4_COM_C_READY_STATUS 0x178 587 584 #define QSERDES_V4_COM_CMN_CONFIG 0x17c 588 585 #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 586 + #define QSERDES_V4_COM_CMN_MISC1 0x19c 587 + #define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 588 + #define QSERDES_V4_COM_CMN_MODE 0x1a4 589 + #define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 589 590 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 590 591 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 591 592 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 592 - #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 593 593 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 594 + #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 594 595 595 596 /* Only for QMP V4 PHY - TX registers */ 596 597 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 ··· 623 616 #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 624 617 #define QSERDES_V4_TX_VMODE_CTRL1 0xe8 625 618 #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 619 + 620 + /* Only for QMP V4_20 PHY - TX registers */ 621 + #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 622 + #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 623 + #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 624 + #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 625 + #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 626 626 627 627 /* Only for QMP V4 PHY - RX registers */ 628 628 #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 ··· 696 682 #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 697 683 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 698 684 #define QSERDES_V4_DP_PHY_STATUS 0x0dc 685 + 686 + /* Only for QMP V4_20 PHY - RX registers */ 687 + #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 688 + #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 689 + #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 690 + #define QSERDES_V4_20_RX_DFE_3 0x110 691 + #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 692 + #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 693 + #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 694 + #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 695 + #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 696 + #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 697 + #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 698 + #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 699 + #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 700 + #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 701 + #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 702 + #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 703 + #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 704 + #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 705 + #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 706 + #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 707 + #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 708 + #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 709 + #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 710 + #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 711 + #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 699 712 700 713 /* Only for QMP V4 PHY - UFS PCS registers */ 701 714 #define QPHY_V4_PCS_UFS_PHY_START 0x000 ··· 1009 968 #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 1010 969 #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 1011 970 971 + /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 972 + #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 973 + #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 974 + #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 975 + #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 976 + 1012 977 /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ 1013 978 #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 1014 979 #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 ··· 1039 992 #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 1040 993 #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 1041 994 #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 995 + 996 + #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 997 + #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 998 + #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 999 + #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 1000 + #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 1001 + #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 1002 + #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 1042 1003 1043 1004 /* Only for QMP V5 PHY - QSERDES COM registers */ 1044 1005 #define QSERDES_V5_COM_PLL_IVCO 0x058