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phy: qcom-qmp: Use phy_status field for the status bit offset

In preparation of the support for v4.20 PCIe PHY in SDX55, use a
separate "phy_status" field for the status bit offset. This is needed
because, the v4.20 PHY uses a different offset for the PHY Status.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210427065400.18958-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Manivannan Sadhasivam and committed by
Vinod Koul 952b702b 04a82a13

+28 -1
+28 -1
drivers/phy/qualcomm/phy-qcom-qmp.c
··· 2525 2525 unsigned int start_ctrl; 2526 2526 unsigned int pwrdn_ctrl; 2527 2527 unsigned int mask_com_pcs_ready; 2528 + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 2529 + unsigned int phy_status; 2528 2530 2529 2531 /* true, if PHY has a separate PHY_COM control block */ 2530 2532 bool has_phy_com_ctrl; ··· 2740 2738 2741 2739 .start_ctrl = SERDES_START | PCS_START, 2742 2740 .pwrdn_ctrl = SW_PWRDN, 2741 + .phy_status = PHYSTATUS, 2743 2742 }; 2744 2743 2745 2744 static const struct qmp_phy_cfg msm8996_pciephy_cfg = { ··· 2766 2763 .start_ctrl = PCS_START | PLL_READY_GATE_EN, 2767 2764 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2768 2765 .mask_com_pcs_ready = PCS_READY, 2766 + .phy_status = PHYSTATUS, 2769 2767 2770 2768 .has_phy_com_ctrl = true, 2771 2769 .has_lane_rst = true, ··· 2796 2792 2797 2793 .start_ctrl = SERDES_START, 2798 2794 .pwrdn_ctrl = SW_PWRDN, 2795 + .phy_status = PHYSTATUS, 2799 2796 2800 2797 .no_pcs_sw_reset = true, 2801 2798 }; ··· 2823 2818 2824 2819 .start_ctrl = SERDES_START | PCS_START, 2825 2820 .pwrdn_ctrl = SW_PWRDN, 2821 + .phy_status = PHYSTATUS, 2826 2822 }; 2827 2823 2828 2824 static const char * const ipq8074_pciephy_clk_l[] = { ··· 2856 2850 2857 2851 .start_ctrl = SERDES_START | PCS_START, 2858 2852 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2853 + .phy_status = PHYSTATUS, 2859 2854 2860 2855 .has_phy_com_ctrl = false, 2861 2856 .has_lane_rst = false, ··· 2919 2912 2920 2913 .start_ctrl = PCS_START | SERDES_START, 2921 2914 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2915 + .phy_status = PHYSTATUS, 2922 2916 2923 2917 .has_pwrdn_delay = true, 2924 2918 .pwrdn_delay_min = 995, /* us */ ··· 2948 2940 2949 2941 .start_ctrl = PCS_START | SERDES_START, 2950 2942 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2943 + .phy_status = PHYSTATUS, 2951 2944 2952 2945 .has_pwrdn_delay = true, 2953 2946 .pwrdn_delay_min = 995, /* us */ ··· 2987 2978 2988 2979 .start_ctrl = PCS_START | SERDES_START, 2989 2980 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2981 + .phy_status = PHYSTATUS, 2990 2982 2991 2983 .has_pwrdn_delay = true, 2992 2984 .pwrdn_delay_min = 995, /* us */ ··· 3026 3016 3027 3017 .start_ctrl = PCS_START | SERDES_START, 3028 3018 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3019 + .phy_status = PHYSTATUS, 3029 3020 3030 3021 .is_dual_lane_phy = true, 3031 3022 .has_pwrdn_delay = true, ··· 3056 3045 3057 3046 .start_ctrl = SERDES_START | PCS_START, 3058 3047 .pwrdn_ctrl = SW_PWRDN, 3048 + .phy_status = PHYSTATUS, 3059 3049 3060 3050 .has_pwrdn_delay = true, 3061 3051 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ··· 3088 3076 3089 3077 .start_ctrl = SERDES_START | PCS_START, 3090 3078 .pwrdn_ctrl = SW_PWRDN, 3079 + .phy_status = PHYSTATUS, 3091 3080 3092 3081 .has_pwrdn_delay = true, 3093 3082 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ··· 3160 3147 3161 3148 .start_ctrl = SERDES_START | PCS_START, 3162 3149 .pwrdn_ctrl = SW_PWRDN, 3150 + .phy_status = PHYSTATUS, 3163 3151 3164 3152 .has_pwrdn_delay = true, 3165 3153 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ··· 3187 3173 3188 3174 .start_ctrl = SERDES_START, 3189 3175 .pwrdn_ctrl = SW_PWRDN, 3176 + .phy_status = PHYSTATUS, 3190 3177 3191 3178 .is_dual_lane_phy = true, 3192 3179 .no_pcs_sw_reset = true, ··· 3215 3200 3216 3201 .start_ctrl = SERDES_START | PCS_START, 3217 3202 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3203 + .phy_status = PHYSTATUS, 3218 3204 }; 3219 3205 3220 3206 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { ··· 3240 3224 3241 3225 .start_ctrl = SERDES_START | PCS_START, 3242 3226 .pwrdn_ctrl = SW_PWRDN, 3227 + .phy_status = PHYSTATUS, 3243 3228 3244 3229 .is_dual_lane_phy = true, 3245 3230 }; ··· 3265 3248 3266 3249 .start_ctrl = SERDES_START, 3267 3250 .pwrdn_ctrl = SW_PWRDN, 3251 + .phy_status = PHYSTATUS, 3268 3252 3269 3253 .is_dual_lane_phy = true, 3270 3254 }; ··· 3292 3274 3293 3275 .start_ctrl = SERDES_START | PCS_START, 3294 3276 .pwrdn_ctrl = SW_PWRDN, 3277 + .phy_status = PHYSTATUS, 3278 + 3295 3279 3296 3280 .has_pwrdn_delay = true, 3297 3281 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ··· 3325 3305 3326 3306 .start_ctrl = SERDES_START | PCS_START, 3327 3307 .pwrdn_ctrl = SW_PWRDN, 3308 + .phy_status = PHYSTATUS, 3328 3309 3329 3310 .has_pwrdn_delay = true, 3330 3311 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ··· 3354 3333 3355 3334 .start_ctrl = SERDES_START | PCS_START, 3356 3335 .pwrdn_ctrl = SW_PWRDN, 3336 + .phy_status = PHYSTATUS, 3357 3337 3358 3338 .has_pwrdn_delay = true, 3359 3339 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ··· 3386 3364 3387 3365 .start_ctrl = SERDES_START | PCS_START, 3388 3366 .pwrdn_ctrl = SW_PWRDN, 3367 + .phy_status = PHYSTATUS, 3389 3368 3390 3369 .has_pwrdn_delay = true, 3391 3370 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ··· 3455 3432 3456 3433 .start_ctrl = SERDES_START | PCS_START, 3457 3434 .pwrdn_ctrl = SW_PWRDN, 3435 + .phy_status = PHYSTATUS, 3458 3436 3459 3437 .has_pwrdn_delay = true, 3460 3438 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ··· 3482 3458 3483 3459 .start_ctrl = SERDES_START, 3484 3460 .pwrdn_ctrl = SW_PWRDN, 3461 + .phy_status = PHYSTATUS, 3485 3462 3486 3463 .is_dual_lane_phy = true, 3487 3464 }; ··· 3509 3484 3510 3485 .start_ctrl = SERDES_START | PCS_START, 3511 3486 .pwrdn_ctrl = SW_PWRDN, 3487 + .phy_status = PHYSTATUS, 3512 3488 3513 3489 .has_pwrdn_delay = true, 3514 3490 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ··· 3541 3515 3542 3516 .start_ctrl = SERDES_START | PCS_START, 3543 3517 .pwrdn_ctrl = SW_PWRDN, 3518 + .phy_status = PHYSTATUS, 3544 3519 3545 3520 .has_pwrdn_delay = true, 3546 3521 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ··· 4409 4382 ready = PCS_READY; 4410 4383 } else { 4411 4384 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 4412 - mask = PHYSTATUS; 4385 + mask = cfg->phy_status; 4413 4386 ready = 0; 4414 4387 } 4415 4388