tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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phy: qcom-qmp-pcie: rename regs layout arrays

Rename regs layouts to follow the QMP PHY version.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221110192248.873973-5-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul bbe207a1 027d16b5

+30 -26
+26 -26
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 74 74 QPHY_LAYOUT_SIZE 75 75 }; 76 76 77 - static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 78 - [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 79 - [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 80 - [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 81 - [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 82 - }; 83 - 84 - static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 77 + static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 85 78 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 86 79 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 87 80 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, 88 81 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 89 82 }; 90 83 91 - static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 84 + static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 92 85 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 93 86 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 94 87 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, ··· 95 102 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 96 103 }; 97 104 98 - static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 105 + static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 99 106 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 100 107 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 101 108 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 102 109 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 110 + }; 111 + 112 + static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 113 + [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 114 + [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 115 + [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 116 + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 103 117 }; 104 118 105 119 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { ··· 1678 1678 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1679 1679 .vreg_list = NULL, 1680 1680 .num_vregs = 0, 1681 - .regs = pciephy_regs_layout, 1681 + .regs = pciephy_v2_regs_layout, 1682 1682 1683 1683 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1684 1684 .phy_status = PHYSTATUS, ··· 1705 1705 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1706 1706 .vreg_list = NULL, 1707 1707 .num_vregs = 0, 1708 - .regs = ipq_pciephy_gen3_regs_layout, 1708 + .regs = pciephy_v4_regs_layout, 1709 1709 1710 1710 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1711 1711 .phy_status = PHYSTATUS, ··· 1734 1734 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1735 1735 .vreg_list = NULL, 1736 1736 .num_vregs = 0, 1737 - .regs = ipq_pciephy_gen3_regs_layout, 1737 + .regs = pciephy_v4_regs_layout, 1738 1738 1739 1739 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1740 1740 .phy_status = PHYSTATUS, ··· 1761 1761 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1762 1762 .vreg_list = qmp_phy_vreg_l, 1763 1763 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1764 - .regs = sdm845_qmp_pciephy_regs_layout, 1764 + .regs = pciephy_v3_regs_layout, 1765 1765 1766 1766 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1767 1767 .phy_status = PHYSTATUS, ··· 1823 1823 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1824 1824 .vreg_list = qmp_phy_vreg_l, 1825 1825 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1826 - .regs = sm8250_pcie_regs_layout, 1826 + .regs = pciephy_v4_regs_layout, 1827 1827 1828 1828 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1829 1829 .phy_status = PHYSTATUS, ··· 1860 1860 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1861 1861 .vreg_list = qmp_phy_vreg_l, 1862 1862 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1863 - .regs = sm8250_pcie_regs_layout, 1863 + .regs = pciephy_v4_regs_layout, 1864 1864 1865 1865 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1866 1866 .phy_status = PHYSTATUS, ··· 1885 1885 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1886 1886 .vreg_list = qmp_phy_vreg_l, 1887 1887 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1888 - .regs = pciephy_regs_layout, 1888 + .regs = pciephy_v3_regs_layout, 1889 1889 1890 1890 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1891 1891 .phy_status = PHYSTATUS, ··· 1914 1914 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1915 1915 .vreg_list = qmp_phy_vreg_l, 1916 1916 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1917 - .regs = sm8250_pcie_regs_layout, 1917 + .regs = pciephy_v4_regs_layout, 1918 1918 1919 1919 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1920 1920 .phy_status = PHYSTATUS, ··· 1949 1949 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1950 1950 .vreg_list = qmp_phy_vreg_l, 1951 1951 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1952 - .regs = sm8250_pcie_regs_layout, 1952 + .regs = pciephy_v5_regs_layout, 1953 1953 1954 1954 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1955 1955 .phy_status = PHYSTATUS, ··· 1984 1984 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1985 1985 .vreg_list = qmp_phy_vreg_l, 1986 1986 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1987 - .regs = sm8250_pcie_regs_layout, 1987 + .regs = pciephy_v5_regs_layout, 1988 1988 1989 1989 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1990 1990 .phy_status = PHYSTATUS, ··· 2022 2022 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2023 2023 .vreg_list = qmp_phy_vreg_l, 2024 2024 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2025 - .regs = sm8250_pcie_regs_layout, 2025 + .regs = pciephy_v5_regs_layout, 2026 2026 2027 2027 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2028 2028 .phy_status = PHYSTATUS, ··· 2049 2049 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2050 2050 .vreg_list = qmp_phy_vreg_l, 2051 2051 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2052 - .regs = sm8250_pcie_regs_layout, 2052 + .regs = pciephy_v4_regs_layout, 2053 2053 2054 2054 .pwrdn_ctrl = SW_PWRDN, 2055 2055 .phy_status = PHYSTATUS_4_20, ··· 2086 2086 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2087 2087 .vreg_list = qmp_phy_vreg_l, 2088 2088 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2089 - .regs = sm8250_pcie_regs_layout, 2089 + .regs = pciephy_v5_regs_layout, 2090 2090 2091 2091 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2092 2092 .phy_status = PHYSTATUS, ··· 2123 2123 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2124 2124 .vreg_list = qmp_phy_vreg_l, 2125 2125 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2126 - .regs = sm8250_pcie_regs_layout, 2126 + .regs = pciephy_v5_regs_layout, 2127 2127 2128 2128 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2129 2129 .phy_status = PHYSTATUS, ··· 2158 2158 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2159 2159 .vreg_list = qmp_phy_vreg_l, 2160 2160 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2161 - .regs = sm8250_pcie_regs_layout, 2161 + .regs = pciephy_v4_regs_layout, 2162 2162 2163 2163 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2164 2164 .phy_status = PHYSTATUS, ··· 2200 2200 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2201 2201 .vreg_list = qmp_phy_vreg_l, 2202 2202 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2203 - .regs = sm8250_pcie_regs_layout, 2203 + .regs = pciephy_v5_regs_layout, 2204 2204 2205 2205 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2206 2206 .phy_status = PHYSTATUS_4_20,
+4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
··· 7 7 #define QCOM_PHY_QMP_PCS_V5_H_ 8 8 9 9 /* Only for QMP V5 PHY - USB/PCIe PCS registers */ 10 + #define QPHY_V5_PCS_SW_RESET 0x000 11 + #define QPHY_V5_PCS_PCS_STATUS1 0x014 12 + #define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040 13 + #define QPHY_V5_PCS_START_CONTROL 0x044 10 14 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4 11 15 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8 12 16 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc