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linux
phy: qcom-qmp-pcie: rework regs layout arrays
Use symbolic names for the values inside reg layout arrays.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221110192248.873973-4-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Vinod Koul
027d16b5
d94b1d07
+20
-16
+16
-16
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+16
-16
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
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};
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static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
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-
[QPHY_SW_RESET] = 0x00,
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-
[QPHY_START_CTRL] = 0x44,
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-
[QPHY_PCS_STATUS] = 0x14,
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-
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
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[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
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[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
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[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
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};
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static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = 0x00,
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[QPHY_START_CTRL] = 0x08,
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[QPHY_PCS_STATUS] = 0x174,
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[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
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[QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
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[QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
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[QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
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};
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static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = 0x00,
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[QPHY_START_CTRL] = 0x08,
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[QPHY_PCS_STATUS] = 0x174,
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[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
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[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
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[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
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[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
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};
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static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
···
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};
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static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = 0x00,
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[QPHY_START_CTRL] = 0x44,
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-
[QPHY_PCS_STATUS] = 0x14,
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[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
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[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
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[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
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[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
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};
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static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
+4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
+4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
···
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#define QCOM_PHY_QMP_PCS_V2_H_
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/* Only for QMP V2 PHY - PCS registers */
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#define QPHY_V2_PCS_SW_RESET 0x000
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#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
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#define QPHY_V2_PCS_START_CONTROL 0x008
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#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
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#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
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#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
···
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#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
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#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
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#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
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#define QPHY_V2_PCS_PCI_PCS_STATUS 0x174 /* PCI */
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#endif