Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
MIPS: Oprofile: Fixup the loose ends in the plumbing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
Ralf Baechle
and committed by
ba339c03
0401572a
+26
-2
arch/mips/kernel/time.c
+26
-2
arch/mips/kernel/time.c
···
507
return IRQ_HANDLED;
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}
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+
int null_perf_irq(struct pt_regs *regs)
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+
{
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return 0;
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+
}
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+
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+
int (*perf_irq)(struct pt_regs *regs) = null_perf_irq;
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+
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EXPORT_SYMBOL(null_perf_irq);
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EXPORT_SYMBOL(perf_irq);
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+
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asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs)
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{
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+
int r2 = cpu_has_mips_r2;
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+
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irq_enter();
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kstat_this_cpu.irqs[irq]++;
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/*
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* Suckage alert:
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* Before R2 of the architecture there was no way to see if a
530
+
* performance counter interrupt was pending, so we have to run the
531
+
* performance counter interrupt handler anyway.
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*/
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if (!r2 || (read_c0_cause() & (1 << 26)))
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if (perf_irq(regs))
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goto out;
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/* we keep interrupt disabled all the time */
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if (!r2 || (read_c0_cause() & (1 << 30)))
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timer_interrupt(irq, NULL, regs);
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+
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out:
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irq_exit();
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}
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+17
-3
arch/mips/mips-boards/generic/time.c
+17
-3
arch/mips/mips-boards/generic/time.c
···
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do_IRQ (mips_cpu_timer_irq, regs);
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}
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irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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if (cpu == 0) {
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/*
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-
* CPU 0 handles the global timer interrupt job and process accounting
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-
* resets count/compare registers to trigger next timer int.
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*/
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-
timer_interrupt(irq, dev_id, regs);
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scroll_display_message();
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} else {
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/* Everyone else needs to reset the timer int here as
···
114
local_timer_interrupt (irq, dev_id, regs);
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}
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return IRQ_HANDLED;
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}
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···
75
do_IRQ (mips_cpu_timer_irq, regs);
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}
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+
extern int null_perf_irq(struct pt_regs *regs);
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+
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extern int (*perf_irq)(struct pt_regs *regs);
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+
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irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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int r2 = cpu_has_mips_r2;
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int cpu = smp_processor_id();
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if (cpu == 0) {
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/*
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* CPU 0 handles the global timer interrupt job and process
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* accounting resets count/compare registers to trigger next
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* timer int.
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*/
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if (!r2 || (read_c0_cause() & (1 << 26)))
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+
if (perf_irq(regs))
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goto out;
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+
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+
/* we keep interrupt disabled all the time */
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if (!r2 || (read_c0_cause() & (1 << 30)))
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timer_interrupt(irq, NULL, regs);
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+
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scroll_display_message();
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} else {
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/* Everyone else needs to reset the timer int here as
···
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local_timer_interrupt (irq, dev_id, regs);
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}
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+
out:
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return IRQ_HANDLED;
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}
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+2
-2
arch/mips/oprofile/op_impl.h
+2
-2
arch/mips/oprofile/op_impl.h
+5
-1
arch/mips/oprofile/op_model_mipsxx.c
+5
-1
arch/mips/oprofile/op_model_mipsxx.c
···
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}
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}
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117
-
static void mipsxx_perfcount_handler(struct pt_regs *regs)
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{
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unsigned int counters = op_model_mipsxx.num_counters;
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unsigned int control;
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unsigned int counter;
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switch (counters) {
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#define HANDLE_COUNTER(n) \
···
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(counter & M_COUNTER_OVERFLOW)) { \
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oprofile_add_sample(regs, n); \
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write_c0_perfcntr ## n(reg.counter[n]); \
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}
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HANDLE_COUNTER(3)
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HANDLE_COUNTER(2)
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HANDLE_COUNTER(1)
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HANDLE_COUNTER(0)
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}
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}
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#define M_CONFIG1_PC (1 << 4)
···
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}
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}
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+
static int mipsxx_perfcount_handler(struct pt_regs *regs)
118
{
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unsigned int counters = op_model_mipsxx.num_counters;
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unsigned int control;
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unsigned int counter;
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+
int handled = 0;
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switch (counters) {
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#define HANDLE_COUNTER(n) \
···
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(counter & M_COUNTER_OVERFLOW)) { \
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oprofile_add_sample(regs, n); \
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write_c0_perfcntr ## n(reg.counter[n]); \
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+
handled = 1; \
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}
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HANDLE_COUNTER(3)
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HANDLE_COUNTER(2)
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HANDLE_COUNTER(1)
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HANDLE_COUNTER(0)
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}
139
+
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+
return handled;
141
}
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#define M_CONFIG1_PC (1 << 4)