tjh.dev / kernel
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MIPS: Reorganize ISA constants strictly as bitmasks. Signed-off-by: Ralf Baechle <ralf@ongar.mips.com>

authored by

Ralf Baechle and committed by
0401572a 11e6df65

+31 -31
unified split
+21 -24
include/asm-mips/cpu-features.h
··· 116 116 #endif 117 117 #endif 118 118 119 + # ifndef cpu_has_mips32r1 120 + # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 121 + # endif 122 + # ifndef cpu_has_mips32r2 123 + # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 124 + # endif 125 + # ifndef cpu_has_mips64r1 126 + # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 127 + # endif 128 + # ifndef cpu_has_mips64r2 129 + # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 130 + # endif 131 + 132 + /* 133 + * Shortcuts ... 134 + */ 135 + #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) 136 + #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) 137 + #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 138 + #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 139 + 119 140 #ifndef cpu_has_dsp 120 141 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 121 142 #endif ··· 165 144 # ifndef cpu_has_64bit_addresses 166 145 # define cpu_has_64bit_addresses 0 167 146 # endif 168 - # ifndef cpu_has_mips32r1 169 - # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 170 - # endif 171 - # ifndef cpu_has_mips32r2 172 - # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 173 - # endif 174 - # ifndef cpu_has_mips64r1 175 - # define cpu_has_mips64r1 0 176 - # endif 177 - # ifndef cpu_has_mips64r2 178 - # define cpu_has_mips64r2 0 179 - # endif 180 147 #endif 181 148 182 149 #ifdef CONFIG_64BIT ··· 182 173 # endif 183 174 # ifndef cpu_has_64bit_addresses 184 175 # define cpu_has_64bit_addresses 1 185 - # endif 186 - # ifndef cpu_has_mips32r1 187 - # define cpu_has_mips32r1 0 188 - # endif 189 - # ifndef cpu_has_mips32r2 190 - # define cpu_has_mips32r2 0 191 - # endif 192 - # ifndef cpu_has_mips64r1 193 - # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 194 - # endif 195 - # ifndef cpu_has_mips64r2 196 - # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 197 176 # endif 198 177 #endif 199 178
+10 -7
include/asm-mips/cpu.h
··· 202 202 * ISA Level encodings 203 203 * 204 204 */ 205 - #define MIPS_CPU_ISA_64BIT 0x00008000 206 - 207 205 #define MIPS_CPU_ISA_I 0x00000001 208 206 #define MIPS_CPU_ISA_II 0x00000002 209 - #define MIPS_CPU_ISA_III (0x00000003 | MIPS_CPU_ISA_64BIT) 210 - #define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT) 211 - #define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT) 207 + #define MIPS_CPU_ISA_III 0x00000003 208 + #define MIPS_CPU_ISA_IV 0x00000004 209 + #define MIPS_CPU_ISA_V 0x00000005 212 210 #define MIPS_CPU_ISA_M32R1 0x00000020 213 211 #define MIPS_CPU_ISA_M32R2 0x00000040 214 - #define MIPS_CPU_ISA_M64R1 (0x00000080 | MIPS_CPU_ISA_64BIT) 215 - #define MIPS_CPU_ISA_M64R2 (0x00000100 | MIPS_CPU_ISA_64BIT) 212 + #define MIPS_CPU_ISA_M64R1 0x00000080 213 + #define MIPS_CPU_ISA_M64R2 0x00000100 214 + 215 + #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ 216 + MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) 217 + #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 218 + MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) 216 219 217 220 /* 218 221 * CPU Option encodings