Merge tag 'samsung-dt-gic-flags-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

+16 -4

arch/arm/boot/dts/exynos3250-pinctrl.dtsi

··· 362 362 363 363 interrupt-controller; 364 364 interrupt-parent = <&gic>; 365 - interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, 366 - <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; 365 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 366 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 367 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 368 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 369 + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 370 + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 371 + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 372 + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 367 373 #interrupt-cells = <2>; 368 374 }; 369 375 ··· 379 373 380 374 interrupt-controller; 381 375 interrupt-parent = <&gic>; 382 - interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, 383 - <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; 376 + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 377 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 378 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 379 + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 380 + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 381 + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 382 + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 383 + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 384 384 #interrupt-cells = <2>; 385 385 }; 386 386

+58 -39

arch/arm/boot/dts/exynos3250.dtsi

··· 20 20 #include "exynos4-cpu-thermal.dtsi" 21 21 #include "exynos-syscon-restart.dtsi" 22 22 #include <dt-bindings/clock/exynos3250.h> 23 + #include <dt-bindings/interrupt-controller/arm-gic.h> 24 + #include <dt-bindings/interrupt-controller/irq.h> 23 25 24 26 / { 25 27 compatible = "samsung,exynos3250"; ··· 213 211 rtc: rtc@10070000 { 214 212 compatible = "samsung,s3c6410-rtc"; 215 213 reg = <0x10070000 0x100>; 216 - interrupts = <0 73 0>, <0 74 0>; 214 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 215 + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 217 216 interrupt-parent = <&pmu_system_controller>; 218 217 status = "disabled"; 219 218 }; ··· 222 219 tmu: tmu@100C0000 { 223 220 compatible = "samsung,exynos3250-tmu"; 224 221 reg = <0x100C0000 0x100>; 225 - interrupts = <0 216 0>; 222 + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 226 223 clocks = <&cmu CLK_TMU_APBIF>; 227 224 clock-names = "tmu_apbif"; 228 225 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 237 234 <0x10482000 0x1000>, 238 235 <0x10484000 0x2000>, 239 236 <0x10486000 0x2000>; 240 - interrupts = <1 9 0xf04>; 237 + interrupts = <GIC_PPI 9 238 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 241 239 }; 242 240 243 241 mct@10050000 { 244 242 compatible = "samsung,exynos4210-mct"; 245 243 reg = <0x10050000 0x800>; 246 - interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, 247 - <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; 244 + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 245 + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 246 + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 247 + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 248 + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 249 + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 250 + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 251 + <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 248 252 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; 249 253 clock-names = "fin_pll", "mct"; 250 254 }; ··· 259 249 pinctrl_1: pinctrl@11000000 { 260 250 compatible = "samsung,exynos3250-pinctrl"; 261 251 reg = <0x11000000 0x1000>; 262 - interrupts = <0 225 0>; 252 + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 263 253 264 254 wakeup-interrupt-controller { 265 255 compatible = "samsung,exynos4210-wakeup-eint"; 266 - interrupts = <0 48 0>; 256 + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 267 257 }; 268 258 }; 269 259 270 260 pinctrl_0: pinctrl@11400000 { 271 261 compatible = "samsung,exynos3250-pinctrl"; 272 262 reg = <0x11400000 0x1000>; 273 - interrupts = <0 240 0>; 263 + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 274 264 }; 275 265 276 266 jpeg: codec@11830000 { 277 267 compatible = "samsung,exynos3250-jpeg"; 278 268 reg = <0x11830000 0x1000>; 279 - interrupts = <0 171 0>; 269 + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 280 270 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; 281 271 clock-names = "jpeg", "sclk"; 282 272 power-domains = <&pd_cam>; ··· 290 280 sysmmu_jpeg: sysmmu@11A60000 { 291 281 compatible = "samsung,exynos-sysmmu"; 292 282 reg = <0x11a60000 0x1000>; 293 - interrupts = <0 156 0>, <0 161 0>; 283 + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 284 + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 294 285 clock-names = "sysmmu", "master"; 295 286 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; 296 287 power-domains = <&pd_cam>; ··· 302 291 compatible = "samsung,exynos3250-fimd"; 303 292 reg = <0x11c00000 0x30000>; 304 293 interrupt-names = "fifo", "vsync", "lcd_sys"; 305 - interrupts = <0 84 0>, <0 85 0>, <0 86 0>; 294 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 295 + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 296 + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 306 297 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 307 298 clock-names = "sclk_fimd", "fimd"; 308 299 power-domains = <&pd_lcd0>; ··· 316 303 dsi_0: dsi@11C80000 { 317 304 compatible = "samsung,exynos3250-mipi-dsi"; 318 305 reg = <0x11C80000 0x10000>; 319 - interrupts = <0 83 0>; 306 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 320 307 samsung,phy-type = <0>; 321 308 power-domains = <&pd_lcd0>; 322 309 phys = <&mipi_phy 1>; ··· 331 318 sysmmu_fimd0: sysmmu@11E20000 { 332 319 compatible = "samsung,exynos-sysmmu"; 333 320 reg = <0x11e20000 0x1000>; 334 - interrupts = <0 80 0>, <0 81 0>; 321 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 322 + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 335 323 clock-names = "sysmmu", "master"; 336 324 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; 337 325 power-domains = <&pd_lcd0>; ··· 342 328 hsotg: hsotg@12480000 { 343 329 compatible = "snps,dwc2"; 344 330 reg = <0x12480000 0x20000>; 345 - interrupts = <0 141 0>; 331 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 346 332 clocks = <&cmu CLK_USBOTG>; 347 333 clock-names = "otg"; 348 334 phys = <&exynos_usbphy 0>; ··· 353 339 mshc_0: mshc@12510000 { 354 340 compatible = "samsung,exynos5420-dw-mshc"; 355 341 reg = <0x12510000 0x1000>; 356 - interrupts = <0 142 0>; 342 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 357 343 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; 358 344 clock-names = "biu", "ciu"; 359 345 fifo-depth = <0x80>; ··· 365 351 mshc_1: mshc@12520000 { 366 352 compatible = "samsung,exynos5420-dw-mshc"; 367 353 reg = <0x12520000 0x1000>; 368 - interrupts = <0 143 0>; 354 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 369 355 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; 370 356 clock-names = "biu", "ciu"; 371 357 fifo-depth = <0x80>; ··· 377 363 mshc_2: mshc@12530000 { 378 364 compatible = "samsung,exynos5250-dw-mshc"; 379 365 reg = <0x12530000 0x1000>; 380 - interrupts = <0 144 0>; 366 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 381 367 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; 382 368 clock-names = "biu", "ciu"; 383 369 fifo-depth = <0x80>; ··· 405 391 pdma0: pdma@12680000 { 406 392 compatible = "arm,pl330", "arm,primecell"; 407 393 reg = <0x12680000 0x1000>; 408 - interrupts = <0 138 0>; 394 + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 409 395 clocks = <&cmu CLK_PDMA0>; 410 396 clock-names = "apb_pclk"; 411 397 #dma-cells = <1>; ··· 416 402 pdma1: pdma@12690000 { 417 403 compatible = "arm,pl330", "arm,primecell"; 418 404 reg = <0x12690000 0x1000>; 419 - interrupts = <0 139 0>; 405 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 420 406 clocks = <&cmu CLK_PDMA1>; 421 407 clock-names = "apb_pclk"; 422 408 #dma-cells = <1>; ··· 429 415 compatible = "samsung,exynos3250-adc", 430 416 "samsung,exynos-adc-v2"; 431 417 reg = <0x126C0000 0x100>; 432 - interrupts = <0 137 0>; 418 + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 433 419 clock-names = "adc", "sclk"; 434 420 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; 435 421 #io-channel-cells = <1>; ··· 441 427 mfc: codec@13400000 { 442 428 compatible = "samsung,mfc-v7"; 443 429 reg = <0x13400000 0x10000>; 444 - interrupts = <0 102 0>; 430 + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 445 431 clock-names = "mfc", "sclk_mfc"; 446 432 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; 447 433 power-domains = <&pd_mfc>; ··· 451 437 sysmmu_mfc: sysmmu@13620000 { 452 438 compatible = "samsung,exynos-sysmmu"; 453 439 reg = <0x13620000 0x1000>; 454 - interrupts = <0 96 0>, <0 98 0>; 440 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 441 + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 455 442 clock-names = "sysmmu", "master"; 456 443 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; 457 444 power-domains = <&pd_mfc>; ··· 462 447 serial_0: serial@13800000 { 463 448 compatible = "samsung,exynos4210-uart"; 464 449 reg = <0x13800000 0x100>; 465 - interrupts = <0 109 0>; 450 + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 466 451 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 467 452 clock-names = "uart", "clk_uart_baud0"; 468 453 pinctrl-names = "default"; ··· 473 458 serial_1: serial@13810000 { 474 459 compatible = "samsung,exynos4210-uart"; 475 460 reg = <0x13810000 0x100>; 476 - interrupts = <0 110 0>; 461 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 477 462 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 478 463 clock-names = "uart", "clk_uart_baud0"; 479 464 pinctrl-names = "default"; ··· 484 469 serial_2: serial@13820000 { 485 470 compatible = "samsung,exynos4210-uart"; 486 471 reg = <0x13820000 0x100>; 487 - interrupts = <0 111 0>; 472 + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 488 473 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; 489 474 clock-names = "uart", "clk_uart_baud0"; 490 475 pinctrl-names = "default"; ··· 497 482 #size-cells = <0>; 498 483 compatible = "samsung,s3c2440-i2c"; 499 484 reg = <0x13860000 0x100>; 500 - interrupts = <0 113 0>; 485 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 501 486 clocks = <&cmu CLK_I2C0>; 502 487 clock-names = "i2c"; 503 488 pinctrl-names = "default"; ··· 510 495 #size-cells = <0>; 511 496 compatible = "samsung,s3c2440-i2c"; 512 497 reg = <0x13870000 0x100>; 513 - interrupts = <0 114 0>; 498 + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 514 499 clocks = <&cmu CLK_I2C1>; 515 500 clock-names = "i2c"; 516 501 pinctrl-names = "default"; ··· 523 508 #size-cells = <0>; 524 509 compatible = "samsung,s3c2440-i2c"; 525 510 reg = <0x13880000 0x100>; 526 - interrupts = <0 115 0>; 511 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 527 512 clocks = <&cmu CLK_I2C2>; 528 513 clock-names = "i2c"; 529 514 pinctrl-names = "default"; ··· 536 521 #size-cells = <0>; 537 522 compatible = "samsung,s3c2440-i2c"; 538 523 reg = <0x13890000 0x100>; 539 - interrupts = <0 116 0>; 524 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 540 525 clocks = <&cmu CLK_I2C3>; 541 526 clock-names = "i2c"; 542 527 pinctrl-names = "default"; ··· 549 534 #size-cells = <0>; 550 535 compatible = "samsung,s3c2440-i2c"; 551 536 reg = <0x138A0000 0x100>; 552 - interrupts = <0 117 0>; 537 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 553 538 clocks = <&cmu CLK_I2C4>; 554 539 clock-names = "i2c"; 555 540 pinctrl-names = "default"; ··· 562 547 #size-cells = <0>; 563 548 compatible = "samsung,s3c2440-i2c"; 564 549 reg = <0x138B0000 0x100>; 565 - interrupts = <0 118 0>; 550 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 566 551 clocks = <&cmu CLK_I2C5>; 567 552 clock-names = "i2c"; 568 553 pinctrl-names = "default"; ··· 575 560 #size-cells = <0>; 576 561 compatible = "samsung,s3c2440-i2c"; 577 562 reg = <0x138C0000 0x100>; 578 - interrupts = <0 119 0>; 563 + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 579 564 clocks = <&cmu CLK_I2C6>; 580 565 clock-names = "i2c"; 581 566 pinctrl-names = "default"; ··· 588 573 #size-cells = <0>; 589 574 compatible = "samsung,s3c2440-i2c"; 590 575 reg = <0x138D0000 0x100>; 591 - interrupts = <0 120 0>; 576 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 592 577 clocks = <&cmu CLK_I2C7>; 593 578 clock-names = "i2c"; 594 579 pinctrl-names = "default"; ··· 599 584 spi_0: spi@13920000 { 600 585 compatible = "samsung,exynos4210-spi"; 601 586 reg = <0x13920000 0x100>; 602 - interrupts = <0 121 0>; 587 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 603 588 dmas = <&pdma0 7>, <&pdma0 6>; 604 589 dma-names = "tx", "rx"; 605 590 #address-cells = <1>; ··· 615 600 spi_1: spi@13930000 { 616 601 compatible = "samsung,exynos4210-spi"; 617 602 reg = <0x13930000 0x100>; 618 - interrupts = <0 122 0>; 603 + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 619 604 dmas = <&pdma1 7>, <&pdma1 6>; 620 605 dma-names = "tx", "rx"; 621 606 #address-cells = <1>; ··· 631 616 i2s2: i2s@13970000 { 632 617 compatible = "samsung,s3c6410-i2s"; 633 618 reg = <0x13970000 0x100>; 634 - interrupts = <0 126 0>; 619 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 635 620 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; 636 621 clock-names = "iis", "i2s_opclk0"; 637 622 dmas = <&pdma0 14>, <&pdma0 13>; ··· 644 629 pwm: pwm@139D0000 { 645 630 compatible = "samsung,exynos4210-pwm"; 646 631 reg = <0x139D0000 0x1000>; 647 - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, 648 - <0 107 0>, <0 108 0>; 632 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 633 + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 634 + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 635 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 636 + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 649 637 #pwm-cells = <3>; 650 638 status = "disabled"; 651 639 }; 652 640 653 641 pmu { 654 642 compatible = "arm,cortex-a7-pmu"; 655 - interrupts = <0 18 0>, <0 19 0>; 643 + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 644 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 656 645 }; 657 646 658 647 ppmu_dmc0: ppmu_dmc0@106a0000 {

+51 -44

arch/arm/boot/dts/exynos4.dtsi

··· 21 21 22 22 #include <dt-bindings/clock/exynos4.h> 23 23 #include <dt-bindings/clock/exynos-audss-clk.h> 24 + #include <dt-bindings/interrupt-controller/arm-gic.h> 25 + #include <dt-bindings/interrupt-controller/irq.h> 24 26 #include "exynos-syscon-restart.dtsi" 25 27 26 28 / { ··· 175 173 dsi_0: dsi@11C80000 { 176 174 compatible = "samsung,exynos4210-mipi-dsi"; 177 175 reg = <0x11C80000 0x10000>; 178 - interrupts = <0 79 0>; 176 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 179 177 power-domains = <&pd_lcd0>; 180 178 phys = <&mipi_phy 1>; 181 179 phy-names = "dsim"; ··· 198 196 fimc_0: fimc@11800000 { 199 197 compatible = "samsung,exynos4210-fimc"; 200 198 reg = <0x11800000 0x1000>; 201 - interrupts = <0 84 0>; 199 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 202 200 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; 203 201 clock-names = "fimc", "sclk_fimc"; 204 202 power-domains = <&pd_cam>; ··· 210 208 fimc_1: fimc@11810000 { 211 209 compatible = "samsung,exynos4210-fimc"; 212 210 reg = <0x11810000 0x1000>; 213 - interrupts = <0 85 0>; 211 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 214 212 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; 215 213 clock-names = "fimc", "sclk_fimc"; 216 214 power-domains = <&pd_cam>; ··· 222 220 fimc_2: fimc@11820000 { 223 221 compatible = "samsung,exynos4210-fimc"; 224 222 reg = <0x11820000 0x1000>; 225 - interrupts = <0 86 0>; 223 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 226 224 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; 227 225 clock-names = "fimc", "sclk_fimc"; 228 226 power-domains = <&pd_cam>; ··· 234 232 fimc_3: fimc@11830000 { 235 233 compatible = "samsung,exynos4210-fimc"; 236 234 reg = <0x11830000 0x1000>; 237 - interrupts = <0 87 0>; 235 + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 238 236 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; 239 237 clock-names = "fimc", "sclk_fimc"; 240 238 power-domains = <&pd_cam>; ··· 246 244 csis_0: csis@11880000 { 247 245 compatible = "samsung,exynos4210-csis"; 248 246 reg = <0x11880000 0x4000>; 249 - interrupts = <0 78 0>; 247 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 250 248 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; 251 249 clock-names = "csis", "sclk_csis"; 252 250 bus-width = <4>; ··· 261 259 csis_1: csis@11890000 { 262 260 compatible = "samsung,exynos4210-csis"; 263 261 reg = <0x11890000 0x4000>; 264 - interrupts = <0 80 0>; 262 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 265 263 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; 266 264 clock-names = "csis", "sclk_csis"; 267 265 bus-width = <2>; ··· 277 275 watchdog: watchdog@10060000 { 278 276 compatible = "samsung,s3c2410-wdt"; 279 277 reg = <0x10060000 0x100>; 280 - interrupts = <0 43 0>; 278 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 281 279 clocks = <&clock CLK_WDT>; 282 280 clock-names = "watchdog"; 283 281 status = "disabled"; ··· 287 285 compatible = "samsung,s3c6410-rtc"; 288 286 reg = <0x10070000 0x100>; 289 287 interrupt-parent = <&pmu_system_controller>; 290 - interrupts = <0 44 0>, <0 45 0>; 288 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 289 + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 291 290 clocks = <&clock CLK_RTC>; 292 291 clock-names = "rtc"; 293 292 status = "disabled"; ··· 297 294 keypad: keypad@100A0000 { 298 295 compatible = "samsung,s5pv210-keypad"; 299 296 reg = <0x100A0000 0x100>; 300 - interrupts = <0 109 0>; 297 + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 301 298 clocks = <&clock CLK_KEYIF>; 302 299 clock-names = "keypad"; 303 300 status = "disabled"; ··· 306 303 sdhci_0: sdhci@12510000 { 307 304 compatible = "samsung,exynos4210-sdhci"; 308 305 reg = <0x12510000 0x100>; 309 - interrupts = <0 73 0>; 306 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 310 307 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 311 308 clock-names = "hsmmc", "mmc_busclk.2"; 312 309 status = "disabled"; ··· 315 312 sdhci_1: sdhci@12520000 { 316 313 compatible = "samsung,exynos4210-sdhci"; 317 314 reg = <0x12520000 0x100>; 318 - interrupts = <0 74 0>; 315 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 319 316 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 320 317 clock-names = "hsmmc", "mmc_busclk.2"; 321 318 status = "disabled"; ··· 324 321 sdhci_2: sdhci@12530000 { 325 322 compatible = "samsung,exynos4210-sdhci"; 326 323 reg = <0x12530000 0x100>; 327 - interrupts = <0 75 0>; 324 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 328 325 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 329 326 clock-names = "hsmmc", "mmc_busclk.2"; 330 327 status = "disabled"; ··· 333 330 sdhci_3: sdhci@12540000 { 334 331 compatible = "samsung,exynos4210-sdhci"; 335 332 reg = <0x12540000 0x100>; 336 - interrupts = <0 76 0>; 333 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 337 334 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 338 335 clock-names = "hsmmc", "mmc_busclk.2"; 339 336 status = "disabled"; ··· 352 349 hsotg: hsotg@12480000 { 353 350 compatible = "samsung,s3c6400-hsotg"; 354 351 reg = <0x12480000 0x20000>; 355 - interrupts = <0 71 0>; 352 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 356 353 clocks = <&clock CLK_USB_DEVICE>; 357 354 clock-names = "otg"; 358 355 phys = <&exynos_usbphy 0>; ··· 363 360 ehci: ehci@12580000 { 364 361 compatible = "samsung,exynos4210-ehci"; 365 362 reg = <0x12580000 0x100>; 366 - interrupts = <0 70 0>; 363 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 367 364 clocks = <&clock CLK_USB_HOST>; 368 365 clock-names = "usbhost"; 369 366 status = "disabled"; ··· 389 386 ohci: ohci@12590000 { 390 387 compatible = "samsung,exynos4210-ohci"; 391 388 reg = <0x12590000 0x100>; 392 - interrupts = <0 70 0>; 389 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 393 390 clocks = <&clock CLK_USB_HOST>; 394 391 clock-names = "usbhost"; 395 392 status = "disabled"; ··· 431 428 mfc: codec@13400000 { 432 429 compatible = "samsung,mfc-v5"; 433 430 reg = <0x13400000 0x10000>; 434 - interrupts = <0 94 0>; 431 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 435 432 power-domains = <&pd_mfc>; 436 433 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; 437 434 clock-names = "mfc", "sclk_mfc"; ··· 442 439 serial_0: serial@13800000 { 443 440 compatible = "samsung,exynos4210-uart"; 444 441 reg = <0x13800000 0x100>; 445 - interrupts = <0 52 0>; 442 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 446 443 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 447 444 clock-names = "uart", "clk_uart_baud0"; 448 445 dmas = <&pdma0 15>, <&pdma0 16>; ··· 453 450 serial_1: serial@13810000 { 454 451 compatible = "samsung,exynos4210-uart"; 455 452 reg = <0x13810000 0x100>; 456 - interrupts = <0 53 0>; 453 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 457 454 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 458 455 clock-names = "uart", "clk_uart_baud0"; 459 456 dmas = <&pdma1 15>, <&pdma1 16>; ··· 464 461 serial_2: serial@13820000 { 465 462 compatible = "samsung,exynos4210-uart"; 466 463 reg = <0x13820000 0x100>; 467 - interrupts = <0 54 0>; 464 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 468 465 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 469 466 clock-names = "uart", "clk_uart_baud0"; 470 467 dmas = <&pdma0 17>, <&pdma0 18>; ··· 475 472 serial_3: serial@13830000 { 476 473 compatible = "samsung,exynos4210-uart"; 477 474 reg = <0x13830000 0x100>; 478 - interrupts = <0 55 0>; 475 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 479 476 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 480 477 clock-names = "uart", "clk_uart_baud0"; 481 478 dmas = <&pdma1 17>, <&pdma1 18>; ··· 488 485 #size-cells = <0>; 489 486 compatible = "samsung,s3c2440-i2c"; 490 487 reg = <0x13860000 0x100>; 491 - interrupts = <0 58 0>; 488 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 492 489 clocks = <&clock CLK_I2C0>; 493 490 clock-names = "i2c"; 494 491 pinctrl-names = "default"; ··· 501 498 #size-cells = <0>; 502 499 compatible = "samsung,s3c2440-i2c"; 503 500 reg = <0x13870000 0x100>; 504 - interrupts = <0 59 0>; 501 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 505 502 clocks = <&clock CLK_I2C1>; 506 503 clock-names = "i2c"; 507 504 pinctrl-names = "default"; ··· 514 511 #size-cells = <0>; 515 512 compatible = "samsung,s3c2440-i2c"; 516 513 reg = <0x13880000 0x100>; 517 - interrupts = <0 60 0>; 514 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 518 515 clocks = <&clock CLK_I2C2>; 519 516 clock-names = "i2c"; 520 517 pinctrl-names = "default"; ··· 527 524 #size-cells = <0>; 528 525 compatible = "samsung,s3c2440-i2c"; 529 526 reg = <0x13890000 0x100>; 530 - interrupts = <0 61 0>; 527 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 531 528 clocks = <&clock CLK_I2C3>; 532 529 clock-names = "i2c"; 533 530 pinctrl-names = "default"; ··· 540 537 #size-cells = <0>; 541 538 compatible = "samsung,s3c2440-i2c"; 542 539 reg = <0x138A0000 0x100>; 543 - interrupts = <0 62 0>; 540 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 544 541 clocks = <&clock CLK_I2C4>; 545 542 clock-names = "i2c"; 546 543 pinctrl-names = "default"; ··· 553 550 #size-cells = <0>; 554 551 compatible = "samsung,s3c2440-i2c"; 555 552 reg = <0x138B0000 0x100>; 556 - interrupts = <0 63 0>; 553 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 557 554 clocks = <&clock CLK_I2C5>; 558 555 clock-names = "i2c"; 559 556 pinctrl-names = "default"; ··· 566 563 #size-cells = <0>; 567 564 compatible = "samsung,s3c2440-i2c"; 568 565 reg = <0x138C0000 0x100>; 569 - interrupts = <0 64 0>; 566 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 570 567 clocks = <&clock CLK_I2C6>; 571 568 clock-names = "i2c"; 572 569 pinctrl-names = "default"; ··· 579 576 #size-cells = <0>; 580 577 compatible = "samsung,s3c2440-i2c"; 581 578 reg = <0x138D0000 0x100>; 582 - interrupts = <0 65 0>; 579 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 583 580 clocks = <&clock CLK_I2C7>; 584 581 clock-names = "i2c"; 585 582 pinctrl-names = "default"; ··· 592 589 #size-cells = <0>; 593 590 compatible = "samsung,s3c2440-hdmiphy-i2c"; 594 591 reg = <0x138E0000 0x100>; 595 - interrupts = <0 93 0>; 592 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 596 593 clocks = <&clock CLK_I2C_HDMI>; 597 594 clock-names = "i2c"; 598 595 status = "disabled"; ··· 606 603 spi_0: spi@13920000 { 607 604 compatible = "samsung,exynos4210-spi"; 608 605 reg = <0x13920000 0x100>; 609 - interrupts = <0 66 0>; 606 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 610 607 dmas = <&pdma0 7>, <&pdma0 6>; 611 608 dma-names = "tx", "rx"; 612 609 #address-cells = <1>; ··· 621 618 spi_1: spi@13930000 { 622 619 compatible = "samsung,exynos4210-spi"; 623 620 reg = <0x13930000 0x100>; 624 - interrupts = <0 67 0>; 621 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 625 622 dmas = <&pdma1 7>, <&pdma1 6>; 626 623 dma-names = "tx", "rx"; 627 624 #address-cells = <1>; ··· 636 633 spi_2: spi@13940000 { 637 634 compatible = "samsung,exynos4210-spi"; 638 635 reg = <0x13940000 0x100>; 639 - interrupts = <0 68 0>; 636 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 640 637 dmas = <&pdma0 9>, <&pdma0 8>; 641 638 dma-names = "tx", "rx"; 642 639 #address-cells = <1>; ··· 651 648 pwm: pwm@139D0000 { 652 649 compatible = "samsung,exynos4210-pwm"; 653 650 reg = <0x139D0000 0x1000>; 654 - interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; 651 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 652 + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 653 + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 654 + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 655 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 655 656 clocks = <&clock CLK_PWM>; 656 657 clock-names = "timers"; 657 658 #pwm-cells = <3>; ··· 672 665 pdma0: pdma@12680000 { 673 666 compatible = "arm,pl330", "arm,primecell"; 674 667 reg = <0x12680000 0x1000>; 675 - interrupts = <0 35 0>; 668 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 676 669 clocks = <&clock CLK_PDMA0>; 677 670 clock-names = "apb_pclk"; 678 671 #dma-cells = <1>; ··· 683 676 pdma1: pdma@12690000 { 684 677 compatible = "arm,pl330", "arm,primecell"; 685 678 reg = <0x12690000 0x1000>; 686 - interrupts = <0 36 0>; 679 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 687 680 clocks = <&clock CLK_PDMA1>; 688 681 clock-names = "apb_pclk"; 689 682 #dma-cells = <1>; ··· 694 687 mdma1: mdma@12850000 { 695 688 compatible = "arm,pl330", "arm,primecell"; 696 689 reg = <0x12850000 0x1000>; 697 - interrupts = <0 34 0>; 690 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 698 691 clocks = <&clock CLK_MDMA>; 699 692 clock-names = "apb_pclk"; 700 693 #dma-cells = <1>; ··· 724 717 jpeg_codec: jpeg-codec@11840000 { 725 718 compatible = "samsung,exynos4210-jpeg"; 726 719 reg = <0x11840000 0x1000>; 727 - interrupts = <0 88 0>; 720 + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 728 721 clocks = <&clock CLK_JPEG>; 729 722 clock-names = "jpeg"; 730 723 power-domains = <&pd_cam>; ··· 734 727 rotator: rotator@12810000 { 735 728 compatible = "samsung,exynos4210-rotator"; 736 729 reg = <0x12810000 0x64>; 737 - interrupts = <0 83 0>; 730 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 738 731 clocks = <&clock CLK_ROTATOR>; 739 732 clock-names = "rotator"; 740 733 iommus = <&sysmmu_rotator>; ··· 743 736 hdmi: hdmi@12D00000 { 744 737 compatible = "samsung,exynos4210-hdmi"; 745 738 reg = <0x12D00000 0x70000>; 746 - interrupts = <0 92 0>; 739 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 747 740 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", 748 741 "mout_hdmi"; 749 742 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, ··· 758 751 hdmicec: cec@100B0000 { 759 752 compatible = "samsung,s5p-cec"; 760 753 reg = <0x100B0000 0x200>; 761 - interrupts = <0 114 0>; 754 + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 762 755 clocks = <&clock CLK_HDMI_CEC>; 763 756 clock-names = "hdmicec"; 764 757 samsung,syscon-phandle = <&pmu_system_controller>; ··· 769 762 770 763 mixer: mixer@12C10000 { 771 764 compatible = "samsung,exynos4210-mixer"; 772 - interrupts = <0 91 0>; 765 + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 773 766 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; 774 767 power-domains = <&pd_tv>; 775 768 iommus = <&sysmmu_tv>; ··· 996 989 sss: sss@10830000 { 997 990 compatible = "samsung,exynos4210-secss"; 998 991 reg = <0x10830000 0x300>; 999 - interrupts = <0 112 0>; 992 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1000 993 clocks = <&clock CLK_SSS>; 1001 994 clock-names = "secss"; 1002 995 };

+16 -4

arch/arm/boot/dts/exynos4210-pinctrl.dtsi

··· 537 537 538 538 interrupt-controller; 539 539 interrupt-parent = <&gic>; 540 - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, 541 - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; 540 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 541 + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 542 + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 543 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 544 + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 545 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 546 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 547 + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 542 548 #interrupt-cells = <2>; 543 549 }; 544 550 ··· 554 548 555 549 interrupt-controller; 556 550 interrupt-parent = <&gic>; 557 - interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, 558 - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; 551 + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 552 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 553 + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 554 + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 555 + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 556 + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 557 + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 558 + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 559 559 #interrupt-cells = <2>; 560 560 }; 561 561

+24 -12

arch/arm/boot/dts/exynos4210.dtsi

··· 109 109 #interrupt-cells = <1>; 110 110 #address-cells = <0>; 111 111 #size-cells = <0>; 112 - interrupt-map = <0 &gic 0 57 0>, 113 - <1 &gic 0 69 0>, 112 + interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, 113 + <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>, 114 114 <2 &combiner 12 6>, 115 115 <3 &combiner 12 7>, 116 - <4 &gic 0 42 0>, 117 - <5 &gic 0 48 0>; 116 + <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>, 117 + <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>; 118 118 }; 119 119 }; 120 120 ··· 127 127 pinctrl_0: pinctrl@11400000 { 128 128 compatible = "samsung,exynos4210-pinctrl"; 129 129 reg = <0x11400000 0x1000>; 130 - interrupts = <0 47 0>; 130 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 131 131 }; 132 132 133 133 pinctrl_1: pinctrl@11000000 { 134 134 compatible = "samsung,exynos4210-pinctrl"; 135 135 reg = <0x11000000 0x1000>; 136 - interrupts = <0 46 0>; 136 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 137 137 138 138 wakup_eint: wakeup-interrupt-controller { 139 139 compatible = "samsung,exynos4210-wakeup-eint"; 140 140 interrupt-parent = <&gic>; 141 - interrupts = <0 32 0>; 141 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 142 142 }; 143 143 }; 144 144 ··· 182 182 g2d: g2d@12800000 { 183 183 compatible = "samsung,s5pv210-g2d"; 184 184 reg = <0x12800000 0x1000>; 185 - interrupts = <0 89 0>; 185 + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 186 186 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 187 187 clock-names = "sclk_fimg2d", "fimg2d"; 188 188 power-domains = <&pd_lcd0>; ··· 424 424 425 425 &combiner { 426 426 samsung,combiner-nr = <16>; 427 - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 428 - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, 429 - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, 430 - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; 427 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 428 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 429 + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 430 + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 431 + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 432 + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 433 + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 434 + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 435 + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 436 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 437 + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 438 + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 439 + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 440 + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 441 + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 442 + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 431 443 }; 432 444 433 445 &mdma1 {

+16 -4

arch/arm/boot/dts/exynos4x12-pinctrl.dtsi

··· 572 572 573 573 interrupt-controller; 574 574 interrupt-parent = <&gic>; 575 - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, 576 - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; 575 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 576 + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 577 + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 578 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 579 + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 580 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 581 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 582 + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 577 583 #interrupt-cells = <2>; 578 584 }; 579 585 ··· 589 583 590 584 interrupt-controller; 591 585 interrupt-parent = <&gic>; 592 - interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, 593 - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; 586 + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 587 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 588 + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 589 + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 590 + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 591 + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 592 + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 593 + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 594 594 #interrupt-cells = <2>; 595 595 }; 596 596

+32 -16

arch/arm/boot/dts/exynos4x12.dtsi

··· 88 88 #interrupt-cells = <1>; 89 89 #address-cells = <0>; 90 90 #size-cells = <0>; 91 - interrupt-map = <0 &gic 0 57 0>, 91 + interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, 92 92 <1 &combiner 12 5>, 93 93 <2 &combiner 12 6>, 94 94 <3 &combiner 12 7>, 95 - <4 &gic 1 12 0>; 95 + <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>; 96 96 }; 97 97 }; 98 98 ··· 112 112 g2d: g2d@10800000 { 113 113 compatible = "samsung,exynos4212-g2d"; 114 114 reg = <0x10800000 0x1000>; 115 - interrupts = <0 89 0>; 115 + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 116 116 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 117 117 clock-names = "sclk_fimg2d", "fimg2d"; 118 118 iommus = <&sysmmu_g2d>; ··· 127 127 fimc_lite_0: fimc-lite@12390000 { 128 128 compatible = "samsung,exynos4212-fimc-lite"; 129 129 reg = <0x12390000 0x1000>; 130 - interrupts = <0 105 0>; 130 + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 131 131 power-domains = <&pd_isp>; 132 132 clocks = <&clock CLK_FIMC_LITE0>; 133 133 clock-names = "flite"; ··· 138 138 fimc_lite_1: fimc-lite@123A0000 { 139 139 compatible = "samsung,exynos4212-fimc-lite"; 140 140 reg = <0x123A0000 0x1000>; 141 - interrupts = <0 106 0>; 141 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 142 142 power-domains = <&pd_isp>; 143 143 clocks = <&clock CLK_FIMC_LITE1>; 144 144 clock-names = "flite"; ··· 149 149 fimc_is: fimc-is@12000000 { 150 150 compatible = "samsung,exynos4212-fimc-is"; 151 151 reg = <0x12000000 0x260000>; 152 - interrupts = <0 90 0>, <0 95 0>; 152 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 153 + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 153 154 power-domains = <&pd_isp>; 154 155 clocks = <&clock CLK_FIMC_LITE0>, 155 156 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, ··· 201 200 mshc_0: mmc@12550000 { 202 201 compatible = "samsung,exynos4412-dw-mshc"; 203 202 reg = <0x12550000 0x1000>; 204 - interrupts = <0 77 0>; 203 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 205 204 #address-cells = <1>; 206 205 #size-cells = <0>; 207 206 fifo-depth = <0x80>; ··· 462 461 }; 463 462 464 463 &combiner { 465 - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 466 - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, 467 - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, 468 - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, 469 - <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; 464 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 465 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 466 + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 467 + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 468 + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 469 + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 470 + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 471 + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 472 + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 473 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 474 + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 475 + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 476 + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 477 + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 478 + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 479 + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 480 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 481 + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 482 + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 483 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 470 484 }; 471 485 472 486 &exynos_usbphy { ··· 545 529 &pinctrl_0 { 546 530 compatible = "samsung,exynos4x12-pinctrl"; 547 531 reg = <0x11400000 0x1000>; 548 - interrupts = <0 47 0>; 532 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 549 533 }; 550 534 551 535 &pinctrl_1 { 552 536 compatible = "samsung,exynos4x12-pinctrl"; 553 537 reg = <0x11000000 0x1000>; 554 - interrupts = <0 46 0>; 538 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 555 539 556 540 wakup_eint: wakeup-interrupt-controller { 557 541 compatible = "samsung,exynos4210-wakeup-eint"; 558 542 interrupt-parent = <&gic>; 559 - interrupts = <0 32 0>; 543 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 560 544 }; 561 545 }; 562 546 ··· 570 554 &pinctrl_3 { 571 555 compatible = "samsung,exynos4x12-pinctrl"; 572 556 reg = <0x106E0000 0x1000>; 573 - interrupts = <0 72 0>; 557 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 574 558 }; 575 559 576 560 &pmu_system_controller {

+46 -18

arch/arm/boot/dts/exynos5.dtsi

··· 13 13 * published by the Free Software Foundation. 14 14 */ 15 15 16 + #include <dt-bindings/interrupt-controller/arm-gic.h> 17 + #include <dt-bindings/interrupt-controller/irq.h> 16 18 #include "exynos-syscon-restart.dtsi" 17 19 18 20 / { ··· 55 53 interrupt-controller; 56 54 samsung,combiner-nr = <32>; 57 55 reg = <0x10440000 0x1000>; 58 - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 59 - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, 60 - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, 61 - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, 62 - <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, 63 - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, 64 - <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, 65 - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; 56 + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, 57 + <0 1 IRQ_TYPE_LEVEL_HIGH>, 58 + <0 2 IRQ_TYPE_LEVEL_HIGH>, 59 + <0 3 IRQ_TYPE_LEVEL_HIGH>, 60 + <0 4 IRQ_TYPE_LEVEL_HIGH>, 61 + <0 5 IRQ_TYPE_LEVEL_HIGH>, 62 + <0 6 IRQ_TYPE_LEVEL_HIGH>, 63 + <0 7 IRQ_TYPE_LEVEL_HIGH>, 64 + <0 8 IRQ_TYPE_LEVEL_HIGH>, 65 + <0 9 IRQ_TYPE_LEVEL_HIGH>, 66 + <0 10 IRQ_TYPE_LEVEL_HIGH>, 67 + <0 11 IRQ_TYPE_LEVEL_HIGH>, 68 + <0 12 IRQ_TYPE_LEVEL_HIGH>, 69 + <0 13 IRQ_TYPE_LEVEL_HIGH>, 70 + <0 14 IRQ_TYPE_LEVEL_HIGH>, 71 + <0 15 IRQ_TYPE_LEVEL_HIGH>, 72 + <0 16 IRQ_TYPE_LEVEL_HIGH>, 73 + <0 17 IRQ_TYPE_LEVEL_HIGH>, 74 + <0 18 IRQ_TYPE_LEVEL_HIGH>, 75 + <0 19 IRQ_TYPE_LEVEL_HIGH>, 76 + <0 20 IRQ_TYPE_LEVEL_HIGH>, 77 + <0 21 IRQ_TYPE_LEVEL_HIGH>, 78 + <0 22 IRQ_TYPE_LEVEL_HIGH>, 79 + <0 23 IRQ_TYPE_LEVEL_HIGH>, 80 + <0 24 IRQ_TYPE_LEVEL_HIGH>, 81 + <0 25 IRQ_TYPE_LEVEL_HIGH>, 82 + <0 26 IRQ_TYPE_LEVEL_HIGH>, 83 + <0 27 IRQ_TYPE_LEVEL_HIGH>, 84 + <0 28 IRQ_TYPE_LEVEL_HIGH>, 85 + <0 29 IRQ_TYPE_LEVEL_HIGH>, 86 + <0 30 IRQ_TYPE_LEVEL_HIGH>, 87 + <0 31 IRQ_TYPE_LEVEL_HIGH>; 66 88 }; 67 89 68 90 gic: interrupt-controller@10481000 { ··· 97 71 <0x10482000 0x1000>, 98 72 <0x10484000 0x2000>, 99 73 <0x10486000 0x2000>; 100 - interrupts = <1 9 0xf04>; 74 + interrupts = <GIC_PPI 9 75 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 101 76 }; 102 77 103 78 sysreg_system_controller: syscon@10050000 { ··· 109 82 serial_0: serial@12C00000 { 110 83 compatible = "samsung,exynos4210-uart"; 111 84 reg = <0x12C00000 0x100>; 112 - interrupts = <0 51 0>; 85 + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; 113 86 }; 114 87 115 88 serial_1: serial@12C10000 { 116 89 compatible = "samsung,exynos4210-uart"; 117 90 reg = <0x12C10000 0x100>; 118 - interrupts = <0 52 0>; 91 + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 119 92 }; 120 93 121 94 serial_2: serial@12C20000 { 122 95 compatible = "samsung,exynos4210-uart"; 123 96 reg = <0x12C20000 0x100>; 124 - interrupts = <0 53 0>; 97 + interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>; 125 98 }; 126 99 127 100 serial_3: serial@12C30000 { 128 101 compatible = "samsung,exynos4210-uart"; 129 102 reg = <0x12C30000 0x100>; 130 - interrupts = <0 54 0>; 103 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; 131 104 }; 132 105 133 106 i2c_0: i2c@12C60000 { 134 107 compatible = "samsung,s3c2440-i2c"; 135 108 reg = <0x12C60000 0x100>; 136 - interrupts = <0 56 0>; 109 + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 137 110 #address-cells = <1>; 138 111 #size-cells = <0>; 139 112 samsung,sysreg-phandle = <&sysreg_system_controller>; ··· 143 116 i2c_1: i2c@12C70000 { 144 117 compatible = "samsung,s3c2440-i2c"; 145 118 reg = <0x12C70000 0x100>; 146 - interrupts = <0 57 0>; 119 + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 147 120 #address-cells = <1>; 148 121 #size-cells = <0>; 149 122 samsung,sysreg-phandle = <&sysreg_system_controller>; ··· 153 126 i2c_2: i2c@12C80000 { 154 127 compatible = "samsung,s3c2440-i2c"; 155 128 reg = <0x12C80000 0x100>; 156 - interrupts = <0 58 0>; 129 + interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; 157 130 #address-cells = <1>; 158 131 #size-cells = <0>; 159 132 samsung,sysreg-phandle = <&sysreg_system_controller>; ··· 163 136 i2c_3: i2c@12C90000 { 164 137 compatible = "samsung,s3c2440-i2c"; 165 138 reg = <0x12C90000 0x100>; 166 - interrupts = <0 59 0>; 139 + interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; 167 140 #address-cells = <1>; 168 141 #size-cells = <0>; 169 142 samsung,sysreg-phandle = <&sysreg_system_controller>; ··· 180 153 rtc: rtc@101E0000 { 181 154 compatible = "samsung,s3c6410-rtc"; 182 155 reg = <0x101E0000 0x100>; 183 - interrupts = <0 43 0>, <0 44 0>; 156 + interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>, 157 + <0 44 IRQ_TYPE_LEVEL_HIGH>; 184 158 status = "disabled"; 185 159 }; 186 160

+40 -40

arch/arm/boot/dts/exynos5250.dtsi

··· 181 181 <0x1 0 &combiner 23 4>, 182 182 <0x2 0 &combiner 25 2>, 183 183 <0x3 0 &combiner 25 3>, 184 - <0x4 0 &gic 0 120 0>, 185 - <0x5 0 &gic 0 121 0>; 184 + <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, 185 + <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>; 186 186 }; 187 187 }; 188 188 ··· 195 195 pinctrl_0: pinctrl@11400000 { 196 196 compatible = "samsung,exynos5250-pinctrl"; 197 197 reg = <0x11400000 0x1000>; 198 - interrupts = <0 46 0>; 198 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 199 199 200 200 wakup_eint: wakeup-interrupt-controller { 201 201 compatible = "samsung,exynos4210-wakeup-eint"; 202 202 interrupt-parent = <&gic>; 203 - interrupts = <0 32 0>; 203 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 204 204 }; 205 205 }; 206 206 207 207 pinctrl_1: pinctrl@13400000 { 208 208 compatible = "samsung,exynos5250-pinctrl"; 209 209 reg = <0x13400000 0x1000>; 210 - interrupts = <0 45 0>; 210 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 211 211 }; 212 212 213 213 pinctrl_2: pinctrl@10d10000 { 214 214 compatible = "samsung,exynos5250-pinctrl"; 215 215 reg = <0x10d10000 0x1000>; 216 - interrupts = <0 50 0>; 216 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 217 217 }; 218 218 219 219 pinctrl_3: pinctrl@03860000 { 220 220 compatible = "samsung,exynos5250-pinctrl"; 221 221 reg = <0x03860000 0x1000>; 222 - interrupts = <0 47 0>; 222 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 223 223 }; 224 224 225 225 pmu_system_controller: system-controller@10040000 { ··· 236 236 watchdog@101D0000 { 237 237 compatible = "samsung,exynos5250-wdt"; 238 238 reg = <0x101D0000 0x100>; 239 - interrupts = <0 42 0>; 239 + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 240 240 clocks = <&clock CLK_WDT>; 241 241 clock-names = "watchdog"; 242 242 samsung,syscon-phandle = <&pmu_system_controller>; ··· 245 245 g2d@10850000 { 246 246 compatible = "samsung,exynos5250-g2d"; 247 247 reg = <0x10850000 0x1000>; 248 - interrupts = <0 91 0>; 248 + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 249 249 clocks = <&clock CLK_G2D>; 250 250 clock-names = "fimg2d"; 251 251 iommus = <&sysmmu_g2d>; ··· 254 254 mfc: codec@11000000 { 255 255 compatible = "samsung,mfc-v6"; 256 256 reg = <0x11000000 0x10000>; 257 - interrupts = <0 96 0>; 257 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 258 258 power-domains = <&pd_mfc>; 259 259 clocks = <&clock CLK_MFC>; 260 260 clock-names = "mfc"; ··· 265 265 rotator: rotator@11C00000 { 266 266 compatible = "samsung,exynos5250-rotator"; 267 267 reg = <0x11C00000 0x64>; 268 - interrupts = <0 84 0>; 268 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 269 269 clocks = <&clock CLK_ROTATOR>; 270 270 clock-names = "rotator"; 271 271 iommus = <&sysmmu_rotator>; ··· 274 274 tmu: tmu@10060000 { 275 275 compatible = "samsung,exynos5250-tmu"; 276 276 reg = <0x10060000 0x100>; 277 - interrupts = <0 65 0>; 277 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 278 278 clocks = <&clock CLK_TMU>; 279 279 clock-names = "tmu_apbif"; 280 280 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 284 284 compatible = "snps,dwc-ahci"; 285 285 samsung,sata-freq = <66>; 286 286 reg = <0x122F0000 0x1ff>; 287 - interrupts = <0 115 0>; 287 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 288 288 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 289 289 clock-names = "sata", "sclk_sata"; 290 290 phys = <&sata_phy>; ··· 306 306 i2c_4: i2c@12CA0000 { 307 307 compatible = "samsung,s3c2440-i2c"; 308 308 reg = <0x12CA0000 0x100>; 309 - interrupts = <0 60 0>; 309 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 310 310 #address-cells = <1>; 311 311 #size-cells = <0>; 312 312 clocks = <&clock CLK_I2C4>; ··· 319 319 i2c_5: i2c@12CB0000 { 320 320 compatible = "samsung,s3c2440-i2c"; 321 321 reg = <0x12CB0000 0x100>; 322 - interrupts = <0 61 0>; 322 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 323 323 #address-cells = <1>; 324 324 #size-cells = <0>; 325 325 clocks = <&clock CLK_I2C5>; ··· 332 332 i2c_6: i2c@12CC0000 { 333 333 compatible = "samsung,s3c2440-i2c"; 334 334 reg = <0x12CC0000 0x100>; 335 - interrupts = <0 62 0>; 335 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 336 336 #address-cells = <1>; 337 337 #size-cells = <0>; 338 338 clocks = <&clock CLK_I2C6>; ··· 345 345 i2c_7: i2c@12CD0000 { 346 346 compatible = "samsung,s3c2440-i2c"; 347 347 reg = <0x12CD0000 0x100>; 348 - interrupts = <0 63 0>; 348 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 349 349 #address-cells = <1>; 350 350 #size-cells = <0>; 351 351 clocks = <&clock CLK_I2C7>; ··· 358 358 i2c_8: i2c@12CE0000 { 359 359 compatible = "samsung,s3c2440-hdmiphy-i2c"; 360 360 reg = <0x12CE0000 0x1000>; 361 - interrupts = <0 64 0>; 361 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 362 362 #address-cells = <1>; 363 363 #size-cells = <0>; 364 364 clocks = <&clock CLK_I2C_HDMI>; ··· 380 380 compatible = "samsung,exynos4210-spi"; 381 381 status = "disabled"; 382 382 reg = <0x12d20000 0x100>; 383 - interrupts = <0 66 0>; 383 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 384 384 dmas = <&pdma0 5 385 385 &pdma0 4>; 386 386 dma-names = "tx", "rx"; ··· 396 396 compatible = "samsung,exynos4210-spi"; 397 397 status = "disabled"; 398 398 reg = <0x12d30000 0x100>; 399 - interrupts = <0 67 0>; 399 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 400 400 dmas = <&pdma1 5 401 401 &pdma1 4>; 402 402 dma-names = "tx", "rx"; ··· 412 412 compatible = "samsung,exynos4210-spi"; 413 413 status = "disabled"; 414 414 reg = <0x12d40000 0x100>; 415 - interrupts = <0 68 0>; 415 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 416 416 dmas = <&pdma0 7 417 417 &pdma0 6>; 418 418 dma-names = "tx", "rx"; ··· 426 426 427 427 mmc_0: mmc@12200000 { 428 428 compatible = "samsung,exynos5250-dw-mshc"; 429 - interrupts = <0 75 0>; 429 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 430 430 #address-cells = <1>; 431 431 #size-cells = <0>; 432 432 reg = <0x12200000 0x1000>; ··· 438 438 439 439 mmc_1: mmc@12210000 { 440 440 compatible = "samsung,exynos5250-dw-mshc"; 441 - interrupts = <0 76 0>; 441 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 442 442 #address-cells = <1>; 443 443 #size-cells = <0>; 444 444 reg = <0x12210000 0x1000>; ··· 450 450 451 451 mmc_2: mmc@12220000 { 452 452 compatible = "samsung,exynos5250-dw-mshc"; 453 - interrupts = <0 77 0>; 453 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 454 454 #address-cells = <1>; 455 455 #size-cells = <0>; 456 456 reg = <0x12220000 0x1000>; ··· 463 463 mmc_3: mmc@12230000 { 464 464 compatible = "samsung,exynos5250-dw-mshc"; 465 465 reg = <0x12230000 0x1000>; 466 - interrupts = <0 78 0>; 466 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 467 467 #address-cells = <1>; 468 468 #size-cells = <0>; 469 469 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; ··· 526 526 usbdrd_dwc3: dwc3@12000000 { 527 527 compatible = "synopsys,dwc3"; 528 528 reg = <0x12000000 0x10000>; 529 - interrupts = <0 72 0>; 529 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 530 530 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 531 531 phy-names = "usb2-phy", "usb3-phy"; 532 532 }; ··· 544 544 ehci: usb@12110000 { 545 545 compatible = "samsung,exynos4210-ehci"; 546 546 reg = <0x12110000 0x100>; 547 - interrupts = <0 71 0>; 547 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 548 548 549 549 clocks = <&clock CLK_USB2>; 550 550 clock-names = "usbhost"; ··· 559 559 ohci: usb@12120000 { 560 560 compatible = "samsung,exynos4210-ohci"; 561 561 reg = <0x12120000 0x100>; 562 - interrupts = <0 71 0>; 562 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 563 563 564 564 clocks = <&clock CLK_USB2>; 565 565 clock-names = "usbhost"; ··· 591 591 pdma0: pdma@121A0000 { 592 592 compatible = "arm,pl330", "arm,primecell"; 593 593 reg = <0x121A0000 0x1000>; 594 - interrupts = <0 34 0>; 594 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 595 595 clocks = <&clock CLK_PDMA0>; 596 596 clock-names = "apb_pclk"; 597 597 #dma-cells = <1>; ··· 602 602 pdma1: pdma@121B0000 { 603 603 compatible = "arm,pl330", "arm,primecell"; 604 604 reg = <0x121B0000 0x1000>; 605 - interrupts = <0 35 0>; 605 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 606 606 clocks = <&clock CLK_PDMA1>; 607 607 clock-names = "apb_pclk"; 608 608 #dma-cells = <1>; ··· 613 613 mdma0: mdma@10800000 { 614 614 compatible = "arm,pl330", "arm,primecell"; 615 615 reg = <0x10800000 0x1000>; 616 - interrupts = <0 33 0>; 616 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 617 617 clocks = <&clock CLK_MDMA0>; 618 618 clock-names = "apb_pclk"; 619 619 #dma-cells = <1>; ··· 624 624 mdma1: mdma@11C10000 { 625 625 compatible = "arm,pl330", "arm,primecell"; 626 626 reg = <0x11C10000 0x1000>; 627 - interrupts = <0 124 0>; 627 + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 628 628 clocks = <&clock CLK_MDMA1>; 629 629 clock-names = "apb_pclk"; 630 630 #dma-cells = <1>; ··· 636 636 gsc_0: gsc@13e00000 { 637 637 compatible = "samsung,exynos5-gsc"; 638 638 reg = <0x13e00000 0x1000>; 639 - interrupts = <0 85 0>; 639 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 640 640 power-domains = <&pd_gsc>; 641 641 clocks = <&clock CLK_GSCL0>; 642 642 clock-names = "gscl"; ··· 646 646 gsc_1: gsc@13e10000 { 647 647 compatible = "samsung,exynos5-gsc"; 648 648 reg = <0x13e10000 0x1000>; 649 - interrupts = <0 86 0>; 649 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 650 650 power-domains = <&pd_gsc>; 651 651 clocks = <&clock CLK_GSCL1>; 652 652 clock-names = "gscl"; ··· 656 656 gsc_2: gsc@13e20000 { 657 657 compatible = "samsung,exynos5-gsc"; 658 658 reg = <0x13e20000 0x1000>; 659 - interrupts = <0 87 0>; 659 + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 660 660 power-domains = <&pd_gsc>; 661 661 clocks = <&clock CLK_GSCL2>; 662 662 clock-names = "gscl"; ··· 666 666 gsc_3: gsc@13e30000 { 667 667 compatible = "samsung,exynos5-gsc"; 668 668 reg = <0x13e30000 0x1000>; 669 - interrupts = <0 88 0>; 669 + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 670 670 power-domains = <&pd_gsc>; 671 671 clocks = <&clock CLK_GSCL3>; 672 672 clock-names = "gscl"; ··· 677 677 compatible = "samsung,exynos4212-hdmi"; 678 678 reg = <0x14530000 0x70000>; 679 679 power-domains = <&pd_disp1>; 680 - interrupts = <0 95 0>; 680 + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 681 681 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 682 682 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 683 683 <&clock CLK_MOUT_HDMI>; ··· 690 690 compatible = "samsung,exynos5250-mixer"; 691 691 reg = <0x14450000 0x10000>; 692 692 power-domains = <&pd_disp1>; 693 - interrupts = <0 94 0>; 693 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 694 694 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 695 695 <&clock CLK_SCLK_HDMI>; 696 696 clock-names = "mixer", "hdmi", "sclk_hdmi"; ··· 706 706 adc: adc@12D10000 { 707 707 compatible = "samsung,exynos-adc-v1"; 708 708 reg = <0x12D10000 0x100>; 709 - interrupts = <0 106 0>; 709 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 710 710 clocks = <&clock CLK_ADC>; 711 711 clock-names = "adc"; 712 712 #io-channel-cells = <1>; ··· 718 718 sss@10830000 { 719 719 compatible = "samsung,exynos4210-secss"; 720 720 reg = <0x10830000 0x300>; 721 - interrupts = <0 112 0>; 721 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 722 722 clocks = <&clock CLK_SSS>; 723 723 clock-names = "secss"; 724 724 };

+27 -16

arch/arm/boot/dts/exynos5260.dtsi

··· 10 10 */ 11 11 12 12 #include <dt-bindings/clock/exynos5260-clk.h> 13 + #include <dt-bindings/interrupt-controller/arm-gic.h> 14 + #include <dt-bindings/interrupt-controller/irq.h> 13 15 14 16 / { 15 17 compatible = "samsung,exynos5260", "samsung,exynos5"; ··· 170 168 <0x10482000 0x1000>, 171 169 <0x10484000 0x2000>, 172 170 <0x10486000 0x2000>; 173 - interrupts = <1 9 0xf04>; 171 + interrupts = <GIC_PPI 9 172 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 174 173 }; 175 174 176 175 chipid: chipid@10000000 { ··· 184 181 reg = <0x100B0000 0x1000>; 185 182 clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; 186 183 clock-names = "fin_pll", "mct"; 187 - interrupts = <0 104 0>, <0 105 0>, <0 106 0>, 188 - <0 107 0>, <0 122 0>, <0 123 0>, 189 - <0 124 0>, <0 125 0>, <0 126 0>, 190 - <0 127 0>, <0 128 0>, <0 129 0>; 184 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 185 + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 186 + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 187 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 188 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 189 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 190 + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 191 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 192 + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 193 + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 194 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 195 + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 191 196 }; 192 197 193 198 cci: cci@10F00000 { ··· 221 210 pinctrl_0: pinctrl@11600000 { 222 211 compatible = "samsung,exynos5260-pinctrl"; 223 212 reg = <0x11600000 0x1000>; 224 - interrupts = <0 79 0>; 213 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 225 214 226 215 wakeup-interrupt-controller { 227 216 compatible = "samsung,exynos4210-wakeup-eint"; 228 217 interrupt-parent = <&gic>; 229 - interrupts = <0 32 0>; 218 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 230 219 }; 231 220 }; 232 221 233 222 pinctrl_1: pinctrl@12290000 { 234 223 compatible = "samsung,exynos5260-pinctrl"; 235 224 reg = <0x12290000 0x1000>; 236 - interrupts = <0 157 0>; 225 + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 237 226 }; 238 227 239 228 pinctrl_2: pinctrl@128B0000 { 240 229 compatible = "samsung,exynos5260-pinctrl"; 241 230 reg = <0x128B0000 0x1000>; 242 - interrupts = <0 243 0>; 231 + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 243 232 }; 244 233 245 234 pmu_system_controller: system-controller@10D50000 { ··· 250 239 uart0: serial@12C00000 { 251 240 compatible = "samsung,exynos4210-uart"; 252 241 reg = <0x12C00000 0x100>; 253 - interrupts = <0 146 0>; 242 + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 254 243 clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; 255 244 clock-names = "uart", "clk_uart_baud0"; 256 245 status = "disabled"; ··· 259 248 uart1: serial@12C10000 { 260 249 compatible = "samsung,exynos4210-uart"; 261 250 reg = <0x12C10000 0x100>; 262 - interrupts = <0 147 0>; 251 + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 263 252 clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; 264 253 clock-names = "uart", "clk_uart_baud0"; 265 254 status = "disabled"; ··· 268 257 uart2: serial@12C20000 { 269 258 compatible = "samsung,exynos4210-uart"; 270 259 reg = <0x12C20000 0x100>; 271 - interrupts = <0 148 0>; 260 + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 272 261 clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; 273 262 clock-names = "uart", "clk_uart_baud0"; 274 263 status = "disabled"; ··· 277 266 uart3: serial@12860000 { 278 267 compatible = "samsung,exynos4210-uart"; 279 268 reg = <0x12860000 0x100>; 280 - interrupts = <0 145 0>; 269 + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 281 270 clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; 282 271 clock-names = "uart", "clk_uart_baud0"; 283 272 status = "disabled"; ··· 286 275 mmc_0: mmc@12140000 { 287 276 compatible = "samsung,exynos5250-dw-mshc"; 288 277 reg = <0x12140000 0x2000>; 289 - interrupts = <0 156 0>; 278 + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 290 279 #address-cells = <1>; 291 280 #size-cells = <0>; 292 281 clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; ··· 298 287 mmc_1: mmc@12150000 { 299 288 compatible = "samsung,exynos5250-dw-mshc"; 300 289 reg = <0x12150000 0x2000>; 301 - interrupts = <0 158 0>; 290 + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 302 291 #address-cells = <1>; 303 292 #size-cells = <0>; 304 293 clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; ··· 310 299 mmc_2: mmc@12160000 { 311 300 compatible = "samsung,exynos5250-dw-mshc"; 312 301 reg = <0x12160000 0x2000>; 313 - interrupts = <0 159 0>; 302 + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 314 303 #address-cells = <1>; 315 304 #size-cells = <0>; 316 305 clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;

+13 -13

arch/arm/boot/dts/exynos5410.dtsi

··· 94 94 tmu_cpu0: tmu@10060000 { 95 95 compatible = "samsung,exynos5420-tmu"; 96 96 reg = <0x10060000 0x100>; 97 - interrupts = <GIC_SPI 65 0>; 97 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 98 98 clocks = <&clock CLK_TMU>; 99 99 clock-names = "tmu_apbif"; 100 100 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 103 103 tmu_cpu1: tmu@10064000 { 104 104 compatible = "samsung,exynos5420-tmu"; 105 105 reg = <0x10064000 0x100>; 106 - interrupts = <GIC_SPI 183 0>; 106 + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 107 107 clocks = <&clock CLK_TMU>; 108 108 clock-names = "tmu_apbif"; 109 109 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 112 112 tmu_cpu2: tmu@10068000 { 113 113 compatible = "samsung,exynos5420-tmu"; 114 114 reg = <0x10068000 0x100>; 115 - interrupts = <GIC_SPI 184 0>; 115 + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 116 116 clocks = <&clock CLK_TMU>; 117 117 clock-names = "tmu_apbif"; 118 118 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 121 121 tmu_cpu3: tmu@1006c000 { 122 122 compatible = "samsung,exynos5420-tmu"; 123 123 reg = <0x1006c000 0x100>; 124 - interrupts = <GIC_SPI 185 0>; 124 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 125 125 clocks = <&clock CLK_TMU>; 126 126 clock-names = "tmu_apbif"; 127 127 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 130 130 mmc_0: mmc@12200000 { 131 131 compatible = "samsung,exynos5250-dw-mshc"; 132 132 reg = <0x12200000 0x1000>; 133 - interrupts = <0 75 0>; 133 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 134 134 #address-cells = <1>; 135 135 #size-cells = <0>; 136 136 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; ··· 142 142 mmc_1: mmc@12210000 { 143 143 compatible = "samsung,exynos5250-dw-mshc"; 144 144 reg = <0x12210000 0x1000>; 145 - interrupts = <0 76 0>; 145 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 146 146 #address-cells = <1>; 147 147 #size-cells = <0>; 148 148 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; ··· 154 154 mmc_2: mmc@12220000 { 155 155 compatible = "samsung,exynos5250-dw-mshc"; 156 156 reg = <0x12220000 0x1000>; 157 - interrupts = <0 77 0>; 157 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 158 158 #address-cells = <1>; 159 159 #size-cells = <0>; 160 160 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; ··· 166 166 pinctrl_0: pinctrl@13400000 { 167 167 compatible = "samsung,exynos5410-pinctrl"; 168 168 reg = <0x13400000 0x1000>; 169 - interrupts = <0 45 0>; 169 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 170 170 171 171 wakeup-interrupt-controller { 172 172 compatible = "samsung,exynos4210-wakeup-eint"; 173 173 interrupt-parent = <&gic>; 174 - interrupts = <0 32 0>; 174 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 175 175 }; 176 176 }; 177 177 178 178 pinctrl_1: pinctrl@14000000 { 179 179 compatible = "samsung,exynos5410-pinctrl"; 180 180 reg = <0x14000000 0x1000>; 181 - interrupts = <0 46 0>; 181 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 182 182 }; 183 183 184 184 pinctrl_2: pinctrl@10d10000 { 185 185 compatible = "samsung,exynos5410-pinctrl"; 186 186 reg = <0x10d10000 0x1000>; 187 - interrupts = <0 50 0>; 187 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 188 188 }; 189 189 190 190 pinctrl_3: pinctrl@03860000 { 191 191 compatible = "samsung,exynos5410-pinctrl"; 192 192 reg = <0x03860000 0x1000>; 193 - interrupts = <0 47 0>; 193 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 194 194 }; 195 195 196 196 amba { ··· 388 388 }; 389 389 390 390 &usbdrd_dwc3_1 { 391 - interrupts = <GIC_SPI 200 0>; 391 + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 392 392 }; 393 393 394 394 &usbdrd_phy1 {

+39 -39

arch/arm/boot/dts/exynos5420.dtsi

··· 193 193 mfc: codec@11000000 { 194 194 compatible = "samsung,mfc-v7"; 195 195 reg = <0x11000000 0x10000>; 196 - interrupts = <0 96 0>; 196 + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 197 197 clocks = <&clock CLK_MFC>; 198 198 clock-names = "mfc"; 199 199 power-domains = <&mfc_pd>; ··· 203 203 204 204 mmc_0: mmc@12200000 { 205 205 compatible = "samsung,exynos5420-dw-mshc-smu"; 206 - interrupts = <0 75 0>; 206 + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 207 207 #address-cells = <1>; 208 208 #size-cells = <0>; 209 209 reg = <0x12200000 0x2000>; ··· 215 215 216 216 mmc_1: mmc@12210000 { 217 217 compatible = "samsung,exynos5420-dw-mshc-smu"; 218 - interrupts = <0 76 0>; 218 + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; 219 219 #address-cells = <1>; 220 220 #size-cells = <0>; 221 221 reg = <0x12210000 0x2000>; ··· 227 227 228 228 mmc_2: mmc@12220000 { 229 229 compatible = "samsung,exynos5420-dw-mshc"; 230 - interrupts = <0 77 0>; 230 + interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; 231 231 #address-cells = <1>; 232 232 #size-cells = <0>; 233 233 reg = <0x12220000 0x1000>; ··· 320 320 pinctrl_0: pinctrl@13400000 { 321 321 compatible = "samsung,exynos5420-pinctrl"; 322 322 reg = <0x13400000 0x1000>; 323 - interrupts = <0 45 0>; 323 + interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 324 324 325 325 wakeup-interrupt-controller { 326 326 compatible = "samsung,exynos4210-wakeup-eint"; 327 327 interrupt-parent = <&gic>; 328 - interrupts = <0 32 0>; 328 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 329 329 }; 330 330 }; 331 331 332 332 pinctrl_1: pinctrl@13410000 { 333 333 compatible = "samsung,exynos5420-pinctrl"; 334 334 reg = <0x13410000 0x1000>; 335 - interrupts = <0 78 0>; 335 + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 336 336 }; 337 337 338 338 pinctrl_2: pinctrl@14000000 { 339 339 compatible = "samsung,exynos5420-pinctrl"; 340 340 reg = <0x14000000 0x1000>; 341 - interrupts = <0 46 0>; 341 + interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 342 342 }; 343 343 344 344 pinctrl_3: pinctrl@14010000 { 345 345 compatible = "samsung,exynos5420-pinctrl"; 346 346 reg = <0x14010000 0x1000>; 347 - interrupts = <0 50 0>; 347 + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; 348 348 }; 349 349 350 350 pinctrl_4: pinctrl@03860000 { 351 351 compatible = "samsung,exynos5420-pinctrl"; 352 352 reg = <0x03860000 0x1000>; 353 - interrupts = <0 47 0>; 353 + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 354 354 }; 355 355 356 356 amba { ··· 363 363 adma: adma@03880000 { 364 364 compatible = "arm,pl330", "arm,primecell"; 365 365 reg = <0x03880000 0x1000>; 366 - interrupts = <0 110 0>; 366 + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 367 367 clocks = <&clock_audss EXYNOS_ADMA>; 368 368 clock-names = "apb_pclk"; 369 369 #dma-cells = <1>; ··· 374 374 pdma0: pdma@121A0000 { 375 375 compatible = "arm,pl330", "arm,primecell"; 376 376 reg = <0x121A0000 0x1000>; 377 - interrupts = <0 34 0>; 377 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 378 378 clocks = <&clock CLK_PDMA0>; 379 379 clock-names = "apb_pclk"; 380 380 #dma-cells = <1>; ··· 385 385 pdma1: pdma@121B0000 { 386 386 compatible = "arm,pl330", "arm,primecell"; 387 387 reg = <0x121B0000 0x1000>; 388 - interrupts = <0 35 0>; 388 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 389 389 clocks = <&clock CLK_PDMA1>; 390 390 clock-names = "apb_pclk"; 391 391 #dma-cells = <1>; ··· 396 396 mdma0: mdma@10800000 { 397 397 compatible = "arm,pl330", "arm,primecell"; 398 398 reg = <0x10800000 0x1000>; 399 - interrupts = <0 33 0>; 399 + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 400 400 clocks = <&clock CLK_MDMA0>; 401 401 clock-names = "apb_pclk"; 402 402 #dma-cells = <1>; ··· 407 407 mdma1: mdma@11C10000 { 408 408 compatible = "arm,pl330", "arm,primecell"; 409 409 reg = <0x11C10000 0x1000>; 410 - interrupts = <0 124 0>; 410 + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; 411 411 clocks = <&clock CLK_MDMA1>; 412 412 clock-names = "apb_pclk"; 413 413 #dma-cells = <1>; ··· 479 479 spi_0: spi@12d20000 { 480 480 compatible = "samsung,exynos4210-spi"; 481 481 reg = <0x12d20000 0x100>; 482 - interrupts = <0 68 0>; 482 + interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>; 483 483 dmas = <&pdma0 5 484 484 &pdma0 4>; 485 485 dma-names = "tx", "rx"; ··· 495 495 spi_1: spi@12d30000 { 496 496 compatible = "samsung,exynos4210-spi"; 497 497 reg = <0x12d30000 0x100>; 498 - interrupts = <0 69 0>; 498 + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 499 499 dmas = <&pdma1 5 500 500 &pdma1 4>; 501 501 dma-names = "tx", "rx"; ··· 511 511 spi_2: spi@12d40000 { 512 512 compatible = "samsung,exynos4210-spi"; 513 513 reg = <0x12d40000 0x100>; 514 - interrupts = <0 70 0>; 514 + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; 515 515 dmas = <&pdma0 7 516 516 &pdma0 6>; 517 517 dma-names = "tx", "rx"; ··· 539 539 dsi@14500000 { 540 540 compatible = "samsung,exynos5410-mipi-dsi"; 541 541 reg = <0x14500000 0x10000>; 542 - interrupts = <0 82 0>; 542 + interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 543 543 phys = <&mipi_phy 1>; 544 544 phy-names = "dsim"; 545 545 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; ··· 552 552 adc: adc@12D10000 { 553 553 compatible = "samsung,exynos-adc-v2"; 554 554 reg = <0x12D10000 0x100>; 555 - interrupts = <0 106 0>; 555 + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 556 556 clocks = <&clock CLK_TSADC>; 557 557 clock-names = "adc"; 558 558 #io-channel-cells = <1>; ··· 564 564 hsi2c_8: i2c@12E00000 { 565 565 compatible = "samsung,exynos5250-hsi2c"; 566 566 reg = <0x12E00000 0x1000>; 567 - interrupts = <0 87 0>; 567 + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; 568 568 #address-cells = <1>; 569 569 #size-cells = <0>; 570 570 pinctrl-names = "default"; ··· 577 577 hsi2c_9: i2c@12E10000 { 578 578 compatible = "samsung,exynos5250-hsi2c"; 579 579 reg = <0x12E10000 0x1000>; 580 - interrupts = <0 88 0>; 580 + interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 581 581 #address-cells = <1>; 582 582 #size-cells = <0>; 583 583 pinctrl-names = "default"; ··· 590 590 hsi2c_10: i2c@12E20000 { 591 591 compatible = "samsung,exynos5250-hsi2c"; 592 592 reg = <0x12E20000 0x1000>; 593 - interrupts = <0 203 0>; 593 + interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>; 594 594 #address-cells = <1>; 595 595 #size-cells = <0>; 596 596 pinctrl-names = "default"; ··· 603 603 hdmi: hdmi@14530000 { 604 604 compatible = "samsung,exynos5420-hdmi"; 605 605 reg = <0x14530000 0x70000>; 606 - interrupts = <0 95 0>; 606 + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 607 607 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 608 608 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 609 609 <&clock CLK_MOUT_HDMI>; ··· 622 622 mixer: mixer@14450000 { 623 623 compatible = "samsung,exynos5420-mixer"; 624 624 reg = <0x14450000 0x10000>; 625 - interrupts = <0 94 0>; 625 + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 626 626 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 627 627 <&clock CLK_SCLK_HDMI>; 628 628 clock-names = "mixer", "hdmi", "sclk_hdmi"; ··· 633 633 rotator: rotator@11C00000 { 634 634 compatible = "samsung,exynos5250-rotator"; 635 635 reg = <0x11C00000 0x64>; 636 - interrupts = <0 84 0>; 636 + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 637 637 clocks = <&clock CLK_ROTATOR>; 638 638 clock-names = "rotator"; 639 639 iommus = <&sysmmu_rotator>; ··· 642 642 gsc_0: video-scaler@13e00000 { 643 643 compatible = "samsung,exynos5-gsc"; 644 644 reg = <0x13e00000 0x1000>; 645 - interrupts = <0 85 0>; 645 + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 646 646 clocks = <&clock CLK_GSCL0>; 647 647 clock-names = "gscl"; 648 648 power-domains = <&gsc_pd>; ··· 652 652 gsc_1: video-scaler@13e10000 { 653 653 compatible = "samsung,exynos5-gsc"; 654 654 reg = <0x13e10000 0x1000>; 655 - interrupts = <0 86 0>; 655 + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 656 656 clocks = <&clock CLK_GSCL1>; 657 657 clock-names = "gscl"; 658 658 power-domains = <&gsc_pd>; ··· 662 662 jpeg_0: jpeg@11F50000 { 663 663 compatible = "samsung,exynos5420-jpeg"; 664 664 reg = <0x11F50000 0x1000>; 665 - interrupts = <0 89 0>; 665 + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 666 666 clock-names = "jpeg"; 667 667 clocks = <&clock CLK_JPEG>; 668 668 iommus = <&sysmmu_jpeg0>; ··· 671 671 jpeg_1: jpeg@11F60000 { 672 672 compatible = "samsung,exynos5420-jpeg"; 673 673 reg = <0x11F60000 0x1000>; 674 - interrupts = <0 168 0>; 674 + interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; 675 675 clock-names = "jpeg"; 676 676 clocks = <&clock CLK_JPEG2>; 677 677 iommus = <&sysmmu_jpeg1>; ··· 691 691 tmu_cpu0: tmu@10060000 { 692 692 compatible = "samsung,exynos5420-tmu"; 693 693 reg = <0x10060000 0x100>; 694 - interrupts = <0 65 0>; 694 + interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; 695 695 clocks = <&clock CLK_TMU>; 696 696 clock-names = "tmu_apbif"; 697 697 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 700 700 tmu_cpu1: tmu@10064000 { 701 701 compatible = "samsung,exynos5420-tmu"; 702 702 reg = <0x10064000 0x100>; 703 - interrupts = <0 183 0>; 703 + interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>; 704 704 clocks = <&clock CLK_TMU>; 705 705 clock-names = "tmu_apbif"; 706 706 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 709 709 tmu_cpu2: tmu@10068000 { 710 710 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 711 711 reg = <0x10068000 0x100>, <0x1006c000 0x4>; 712 - interrupts = <0 184 0>; 712 + interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 713 713 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; 714 714 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 715 715 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 718 718 tmu_cpu3: tmu@1006c000 { 719 719 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 720 720 reg = <0x1006c000 0x100>, <0x100a0000 0x4>; 721 - interrupts = <0 185 0>; 721 + interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; 722 722 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; 723 723 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 724 724 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 727 727 tmu_gpu: tmu@100a0000 { 728 728 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 729 729 reg = <0x100a0000 0x100>, <0x10068000 0x4>; 730 - interrupts = <0 215 0>; 730 + interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>; 731 731 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; 732 732 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 733 733 #include "exynos4412-tmu-sensor-conf.dtsi" ··· 799 799 sysmmu_scaler1r: sysmmu@0x12890000 { 800 800 compatible = "samsung,exynos-sysmmu"; 801 801 reg = <0x12890000 0x1000>; 802 - interrupts = <0 186 0>; 802 + interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; 803 803 clock-names = "sysmmu", "master"; 804 804 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 805 805 #iommu-cells = <0>; ··· 808 808 sysmmu_scaler2r: sysmmu@0x128A0000 { 809 809 compatible = "samsung,exynos-sysmmu"; 810 810 reg = <0x128A0000 0x1000>; 811 - interrupts = <0 188 0>; 811 + interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; 812 812 clock-names = "sysmmu", "master"; 813 813 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 814 814 #iommu-cells = <0>; ··· 867 867 sysmmu_jpeg1: sysmmu@0x11F20000 { 868 868 compatible = "samsung,exynos-sysmmu"; 869 869 reg = <0x11F20000 0x1000>; 870 - interrupts = <0 169 0>; 870 + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 871 871 clock-names = "sysmmu", "master"; 872 872 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; 873 873 #iommu-cells = <0>; ··· 1445 1445 }; 1446 1446 1447 1447 &usbdrd_dwc3_1 { 1448 - interrupts = <GIC_SPI 73 0>; 1448 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1449 1449 }; 1450 1450 1451 1451 &usbdrd_phy1 {

+42 -28

arch/arm/boot/dts/exynos5440.dtsi

··· 10 10 */ 11 11 12 12 #include <dt-bindings/clock/exynos5440.h> 13 + #include <dt-bindings/interrupt-controller/arm-gic.h> 14 + #include <dt-bindings/interrupt-controller/irq.h> 13 15 14 16 / { 15 17 compatible = "samsung,exynos5440", "samsung,exynos5"; ··· 43 41 <0x2E2000 0x1000>, 44 42 <0x2E4000 0x2000>, 45 43 <0x2E6000 0x2000>; 46 - interrupts = <1 9 0xf04>; 44 + interrupts = <GIC_PPI 9 45 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 47 46 }; 48 47 49 48 cpus { ··· 75 72 76 73 arm-pmu { 77 74 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; 78 - interrupts = <0 52 4>, 79 - <0 53 4>, 80 - <0 54 4>, 81 - <0 55 4>; 75 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 76 + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 77 + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 78 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 82 79 }; 83 80 84 81 timer { 85 82 compatible = "arm,cortex-a15-timer", 86 83 "arm,armv7-timer"; 87 - interrupts = <1 13 0xf08>, 88 - <1 14 0xf08>, 89 - <1 11 0xf08>, 90 - <1 10 0xf08>; 84 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 85 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 86 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 87 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 91 88 clock-frequency = <50000000>; 92 89 }; 93 90 94 91 cpufreq@160000 { 95 92 compatible = "samsung,exynos5440-cpufreq"; 96 93 reg = <0x160000 0x1000>; 97 - interrupts = <0 57 0>; 94 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 98 95 operating-points = < 99 96 /* KHz uV */ 100 97 1500000 1100000 ··· 111 108 serial_0: serial@B0000 { 112 109 compatible = "samsung,exynos4210-uart"; 113 110 reg = <0xB0000 0x1000>; 114 - interrupts = <0 2 0>; 111 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 115 112 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; 116 113 clock-names = "uart", "clk_uart_baud0"; 117 114 }; ··· 119 116 serial_1: serial@C0000 { 120 117 compatible = "samsung,exynos4210-uart"; 121 118 reg = <0xC0000 0x1000>; 122 - interrupts = <0 3 0>; 119 + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 123 120 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; 124 121 clock-names = "uart", "clk_uart_baud0"; 125 122 }; ··· 127 124 spi_0: spi@D0000 { 128 125 compatible = "samsung,exynos5440-spi"; 129 126 reg = <0xD0000 0x100>; 130 - interrupts = <0 4 0>; 127 + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 131 128 #address-cells = <1>; 132 129 #size-cells = <0>; 133 130 samsung,spi-src-clk = <0>; ··· 139 136 pin_ctrl: pinctrl@E0000 { 140 137 compatible = "samsung,exynos5440-pinctrl"; 141 138 reg = <0xE0000 0x1000>; 142 - interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, 143 - <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>; 139 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 140 + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 141 + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 142 + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 143 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 144 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 145 + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 146 + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 144 147 interrupt-controller; 145 148 #interrupt-cells = <2>; 146 149 #gpio-cells = <2>; ··· 171 162 i2c@F0000 { 172 163 compatible = "samsung,exynos5440-i2c"; 173 164 reg = <0xF0000 0x1000>; 174 - interrupts = <0 5 0>; 165 + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 175 166 #address-cells = <1>; 176 167 #size-cells = <0>; 177 168 clocks = <&clock CLK_B_125>; ··· 181 172 i2c@100000 { 182 173 compatible = "samsung,exynos5440-i2c"; 183 174 reg = <0x100000 0x1000>; 184 - interrupts = <0 6 0>; 175 + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 185 176 #address-cells = <1>; 186 177 #size-cells = <0>; 187 178 clocks = <&clock CLK_B_125>; ··· 191 182 watchdog@110000 { 192 183 compatible = "samsung,s3c2410-wdt"; 193 184 reg = <0x110000 0x1000>; 194 - interrupts = <0 1 0>; 185 + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 195 186 clocks = <&clock CLK_B_125>; 196 187 clock-names = "watchdog"; 197 188 }; ··· 200 191 compatible = "snps,dwmac-3.70a"; 201 192 reg = <0x00230000 0x8000>; 202 193 interrupt-parent = <&gic>; 203 - interrupts = <0 31 4>; 194 + interrupts = <GIC_SPI 31 4>; 204 195 interrupt-names = "macirq"; 205 196 phy-mode = "sgmii"; 206 197 clocks = <&clock CLK_GMAC0>; ··· 218 209 rtc@130000 { 219 210 compatible = "samsung,s3c6410-rtc"; 220 211 reg = <0x130000 0x1000>; 221 - interrupts = <0 17 0>, <0 16 0>; 212 + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 213 + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 222 214 clocks = <&clock CLK_B_125>; 223 215 clock-names = "rtc"; 224 216 }; ··· 227 217 tmuctrl_0: tmuctrl@160118 { 228 218 compatible = "samsung,exynos5440-tmu"; 229 219 reg = <0x160118 0x230>, <0x160368 0x10>; 230 - interrupts = <0 58 0>; 220 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 231 221 clocks = <&clock CLK_B_125>; 232 222 clock-names = "tmu_apbif"; 233 223 #include "exynos5440-tmu-sensor-conf.dtsi" ··· 236 226 tmuctrl_1: tmuctrl@16011C { 237 227 compatible = "samsung,exynos5440-tmu"; 238 228 reg = <0x16011C 0x230>, <0x160368 0x10>; 239 - interrupts = <0 58 0>; 229 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 240 230 clocks = <&clock CLK_B_125>; 241 231 clock-names = "tmu_apbif"; 242 232 #include "exynos5440-tmu-sensor-conf.dtsi" ··· 245 235 tmuctrl_2: tmuctrl@160120 { 246 236 compatible = "samsung,exynos5440-tmu"; 247 237 reg = <0x160120 0x230>, <0x160368 0x10>; 248 - interrupts = <0 58 0>; 238 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 249 239 clocks = <&clock CLK_B_125>; 250 240 clock-names = "tmu_apbif"; 251 241 #include "exynos5440-tmu-sensor-conf.dtsi" ··· 269 259 sata@210000 { 270 260 compatible = "snps,exynos5440-ahci"; 271 261 reg = <0x210000 0x10000>; 272 - interrupts = <0 30 0>; 262 + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 273 263 clocks = <&clock CLK_SATA>; 274 264 clock-names = "sata"; 275 265 }; ··· 277 267 ohci@220000 { 278 268 compatible = "samsung,exynos5440-ohci"; 279 269 reg = <0x220000 0x1000>; 280 - interrupts = <0 29 0>; 270 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 281 271 clocks = <&clock CLK_USB>; 282 272 clock-names = "usbhost"; 283 273 }; ··· 285 275 ehci@221000 { 286 276 compatible = "samsung,exynos5440-ehci"; 287 277 reg = <0x221000 0x1000>; 288 - interrupts = <0 29 0>; 278 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 289 279 clocks = <&clock CLK_USB>; 290 280 clock-names = "usbhost"; 291 281 }; ··· 295 285 reg = <0x290000 0x1000 296 286 0x270000 0x1000 297 287 0x271000 0x40>; 298 - interrupts = <0 20 0>, <0 21 0>, <0 22 0>; 288 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 289 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 290 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 299 291 clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; 300 292 clock-names = "pcie", "pcie_bus"; 301 293 #address-cells = <3>; ··· 318 306 reg = <0x2a0000 0x1000 319 307 0x272000 0x1000 320 308 0x271040 0x40>; 321 - interrupts = <0 23 0>, <0 24 0>, <0 25 0>; 309 + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 310 + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 311 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 322 312 clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; 323 313 clock-names = "pcie", "pcie_bus"; 324 314 #address-cells = <3>;

+17 -17

arch/arm/boot/dts/exynos54xx.dtsi

··· 62 62 <1 &combiner 23 4>, 63 63 <2 &combiner 25 2>, 64 64 <3 &combiner 25 3>, 65 - <4 &gic 0 120 0>, 66 - <5 &gic 0 121 0>, 67 - <6 &gic 0 122 0>, 68 - <7 &gic 0 123 0>, 69 - <8 &gic 0 128 0>, 70 - <9 &gic 0 129 0>, 71 - <10 &gic 0 130 0>, 72 - <11 &gic 0 131 0>; 65 + <4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, 66 + <5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>, 67 + <6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>, 68 + <7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>, 69 + <8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>, 70 + <9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>, 71 + <10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>, 72 + <11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; 73 73 }; 74 74 }; 75 75 76 76 watchdog: watchdog@101d0000 { 77 77 compatible = "samsung,exynos5420-wdt"; 78 78 reg = <0x101d0000 0x100>; 79 - interrupts = <0 42 0>; 79 + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 80 80 }; 81 81 82 82 sss: sss@10830000 { 83 83 compatible = "samsung,exynos4210-secss"; 84 84 reg = <0x10830000 0x300>; 85 - interrupts = <0 112 0>; 85 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 86 86 }; 87 87 88 88 /* i2c_0-3 are defined in exynos5.dtsi */ 89 89 hsi2c_4: i2c@12ca0000 { 90 90 compatible = "samsung,exynos5250-hsi2c"; 91 91 reg = <0x12ca0000 0x1000>; 92 - interrupts = <0 60 0>; 92 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 93 93 #address-cells = <1>; 94 94 #size-cells = <0>; 95 95 status = "disabled"; ··· 98 98 hsi2c_5: i2c@12cb0000 { 99 99 compatible = "samsung,exynos5250-hsi2c"; 100 100 reg = <0x12cb0000 0x1000>; 101 - interrupts = <0 61 0>; 101 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 102 102 #address-cells = <1>; 103 103 #size-cells = <0>; 104 104 status = "disabled"; ··· 107 107 hsi2c_6: i2c@12cc0000 { 108 108 compatible = "samsung,exynos5250-hsi2c"; 109 109 reg = <0x12cc0000 0x1000>; 110 - interrupts = <0 62 0>; 110 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 111 111 #address-cells = <1>; 112 112 #size-cells = <0>; 113 113 status = "disabled"; ··· 116 116 hsi2c_7: i2c@12cd0000 { 117 117 compatible = "samsung,exynos5250-hsi2c"; 118 118 reg = <0x12cd0000 0x1000>; 119 - interrupts = <0 63 0>; 119 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 120 120 #address-cells = <1>; 121 121 #size-cells = <0>; 122 122 status = "disabled"; ··· 131 131 usbdrd_dwc3_0: dwc3@12000000 { 132 132 compatible = "snps,dwc3"; 133 133 reg = <0x12000000 0x10000>; 134 - interrupts = <0 72 0>; 134 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 135 135 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; 136 136 phy-names = "usb2-phy", "usb3-phy"; 137 137 }; ··· 166 166 usbhost2: usb@12110000 { 167 167 compatible = "samsung,exynos4210-ehci"; 168 168 reg = <0x12110000 0x100>; 169 - interrupts = <0 71 0>; 169 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 170 170 171 171 #address-cells = <1>; 172 172 #size-cells = <0>; ··· 179 179 usbhost1: usb@12120000 { 180 180 compatible = "samsung,exynos4210-ohci"; 181 181 reg = <0x12120000 0x100>; 182 - interrupts = <0 71 0>; 182 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 183 183 184 184 #address-cells = <1>; 185 185 #size-cells = <0>;