tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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MIPS: Introduce machinery for testing for MIPSxxR1/2. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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Ralf Baechle and committed by
b4672d37 e7958bb9

+95 -9
unified split
+30 -5
arch/mips/kernel/cpu-probe.c
··· 435 } 436 } 437 438 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 439 { 440 unsigned int config0; ··· 450 isa = (config0 & MIPS_CONF_AT) >> 13; 451 switch (isa) { 452 case 0: 453 - c->isa_level = MIPS_CPU_ISA_M32R1; 454 break; 455 case 2: 456 - c->isa_level = MIPS_CPU_ISA_M64R1; 457 break; 458 default: 459 - panic("Unsupported ISA type, cp0.config0.at: %d.", isa); 460 } 461 462 return config0 & MIPS_CONF_M; 463 } 464 465 static inline unsigned int decode_config1(struct cpuinfo_mips *c) ··· 592 break; 593 case PRID_IMP_34K: 594 c->cputype = CPU_34K; 595 - c->isa_level = MIPS_CPU_ISA_M32R1; 596 break; 597 } 598 } ··· 714 c->fpu_id = cpu_get_fpu_id(); 715 716 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 717 - c->isa_level == MIPS_CPU_ISA_M64R1) { 718 if (c->fpu_id & MIPS_FPIR_3D) 719 c->ases |= MIPS_ASE_MIPS3D; 720 }
··· 435 } 436 } 437 438 + static char unknown_isa[] __initdata = KERN_ERR \ 439 + "Unsupported ISA type, c0.config0: %d."; 440 + 441 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 442 { 443 unsigned int config0; ··· 447 isa = (config0 & MIPS_CONF_AT) >> 13; 448 switch (isa) { 449 case 0: 450 + switch ((config0 >> 10) & 7) { 451 + case 0: 452 + c->isa_level = MIPS_CPU_ISA_M32R1; 453 + break; 454 + case 1: 455 + c->isa_level = MIPS_CPU_ISA_M32R2; 456 + break; 457 + default: 458 + goto unknown; 459 + } 460 break; 461 case 2: 462 + switch ((config0 >> 10) & 7) { 463 + case 0: 464 + c->isa_level = MIPS_CPU_ISA_M64R1; 465 + break; 466 + case 1: 467 + c->isa_level = MIPS_CPU_ISA_M64R2; 468 + break; 469 + default: 470 + goto unknown; 471 + } 472 break; 473 default: 474 + goto unknown; 475 } 476 477 return config0 & MIPS_CONF_M; 478 + 479 + unknown: 480 + panic(unknown_isa, config0); 481 } 482 483 static inline unsigned int decode_config1(struct cpuinfo_mips *c) ··· 568 break; 569 case PRID_IMP_34K: 570 c->cputype = CPU_34K; 571 break; 572 } 573 } ··· 691 c->fpu_id = cpu_get_fpu_id(); 692 693 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 694 + c->isa_level == MIPS_CPU_ISA_M32R2 || 695 + c->isa_level == MIPS_CPU_ISA_M64R1 || 696 + c->isa_level == MIPS_CPU_ISA_M64R2) { 697 if (c->fpu_id & MIPS_FPIR_3D) 698 c->ases |= MIPS_ASE_MIPS3D; 699 }
+3 -3
arch/mips/kernel/time.c
··· 628 mips_hpt_init = c0_hpt_init; 629 } 630 631 - if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32R1) || 632 - (current_cpu_data.isa_level == MIPS_CPU_ISA_I) || 633 - (current_cpu_data.isa_level == MIPS_CPU_ISA_II)) 634 /* 635 * We need to calibrate the counter but we don't have 636 * 64-bit division.
··· 628 mips_hpt_init = c0_hpt_init; 629 } 630 631 + if (cpu_has_mips32r1 || cpu_has_mips32r2 || 632 + (current_cpu_data.isa_level == MIPS_CPU_ISA_I) || 633 + (current_cpu_data.isa_level == MIPS_CPU_ISA_II)) 634 /* 635 * We need to calibrate the counter but we don't have 636 * 64-bit division.
+24
include/asm-mips/cpu-features.h
··· 144 # ifndef cpu_has_64bit_addresses 145 # define cpu_has_64bit_addresses 0 146 # endif 147 #endif 148 149 #ifdef CONFIG_64BIT ··· 173 # endif 174 # ifndef cpu_has_64bit_addresses 175 # define cpu_has_64bit_addresses 1 176 # endif 177 #endif 178
··· 144 # ifndef cpu_has_64bit_addresses 145 # define cpu_has_64bit_addresses 0 146 # endif 147 + # ifndef cpu_has_mips32r1 148 + # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 149 + # endif 150 + # ifndef cpu_has_mips32r2 151 + # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 152 + # endif 153 + # ifndef cpu_has_mips64r1 154 + # define cpu_has_mips64r1 0 155 + # endif 156 + # ifndef cpu_has_mips64r2 157 + # define cpu_has_mips64r2 0 158 + # endif 159 #endif 160 161 #ifdef CONFIG_64BIT ··· 161 # endif 162 # ifndef cpu_has_64bit_addresses 163 # define cpu_has_64bit_addresses 1 164 + # endif 165 + # ifndef cpu_has_mips32r1 166 + # define cpu_has_mips32r1 0 167 + # endif 168 + # ifndef cpu_has_mips32r2 169 + # define cpu_has_mips32r2 0 170 + # endif 171 + # ifndef cpu_has_mips64r1 172 + # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 173 + # endif 174 + # ifndef cpu_has_mips64r2 175 + # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 176 # endif 177 #endif 178
+3 -1
include/asm-mips/cpu.h
··· 210 #define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT) 211 #define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT) 212 #define MIPS_CPU_ISA_M32R1 0x00000020 213 - #define MIPS_CPU_ISA_M64R1 (0x00000040 | MIPS_CPU_ISA_64BIT) 214 215 /* 216 * CPU Option encodings
··· 210 #define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT) 211 #define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT) 212 #define MIPS_CPU_ISA_M32R1 0x00000020 213 + #define MIPS_CPU_ISA_M32R2 0x00000040 214 + #define MIPS_CPU_ISA_M64R1 (0x00000080 | MIPS_CPU_ISA_64BIT) 215 + #define MIPS_CPU_ISA_M64R2 (0x00000100 | MIPS_CPU_ISA_64BIT) 216 217 /* 218 * CPU Option encodings
+5
include/asm-mips/mach-ip22/cpu-feature-overrides.h
··· 34 #define cpu_has_nofpuex 0 35 #define cpu_has_64bits 1 36 37 #endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
··· 34 #define cpu_has_nofpuex 0 35 #define cpu_has_64bits 1 36 37 + #define cpu_has_mips32r1 0 38 + #define cpu_has_mips32r2 0 39 + #define cpu_has_mips64r1 0 40 + #define cpu_has_mips64r2 0 41 + 42 #endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
+5
include/asm-mips/mach-ip27/cpu-feature-overrides.h
··· 37 #define cpu_icache_line_size() 64 38 #define cpu_scache_line_size() 128 39 40 #endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
··· 37 #define cpu_icache_line_size() 64 38 #define cpu_scache_line_size() 128 39 40 + #define cpu_has_mips32r1 0 41 + #define cpu_has_mips32r2 0 42 + #define cpu_has_mips64r1 0 43 + #define cpu_has_mips64r2 0 44 + 45 #endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
+5
include/asm-mips/mach-ip32/cpu-feature-overrides.h
··· 39 #define cpu_has_ic_fills_f_dc 0 40 #define cpu_has_dsp 0 41 42 #endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
··· 39 #define cpu_has_ic_fills_f_dc 0 40 #define cpu_has_dsp 0 41 42 + #define cpu_has_mips32r1 0 43 + #define cpu_has_mips32r2 0 44 + #define cpu_has_mips64r1 0 45 + #define cpu_has_mips64r2 0 46 + 47 #endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
+5
include/asm-mips/mach-ja/cpu-feature-overrides.h
··· 37 #define cpu_icache_line_size() 32 38 #define cpu_scache_line_size() 32 39 40 #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
··· 37 #define cpu_icache_line_size() 32 38 #define cpu_scache_line_size() 32 39 40 + #define cpu_has_mips32r1 0 41 + #define cpu_has_mips32r2 0 42 + #define cpu_has_mips64r1 0 43 + #define cpu_has_mips64r2 0 44 + 45 #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
+5
include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
··· 40 #define cpu_icache_line_size() 32 41 #define cpu_scache_line_size() 32 42 43 #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
··· 40 #define cpu_icache_line_size() 32 41 #define cpu_scache_line_size() 32 42 43 + #define cpu_has_mips32r1 0 44 + #define cpu_has_mips32r2 0 45 + #define cpu_has_mips64r1 0 46 + #define cpu_has_mips64r2 0 47 + 48 #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
+5
include/asm-mips/mach-rm200/cpu-feature-overrides.h
··· 40 #define cpu_icache_line_size() 32 41 #define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */ 42 43 #endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
··· 40 #define cpu_icache_line_size() 32 41 #define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */ 42 43 + #define cpu_has_mips32r1 0 44 + #define cpu_has_mips32r2 0 45 + #define cpu_has_mips64r1 0 46 + #define cpu_has_mips64r2 0 47 + 48 #endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
+5
include/asm-mips/mach-yosemite/cpu-feature-overrides.h
··· 37 #define cpu_icache_line_size() 32 38 #define cpu_scache_line_size() 32 39 40 #endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
··· 37 #define cpu_icache_line_size() 32 38 #define cpu_scache_line_size() 32 39 40 + #define cpu_has_mips32r1 0 41 + #define cpu_has_mips32r2 0 42 + #define cpu_has_mips64r1 0 43 + #define cpu_has_mips64r2 0 44 + 45 #endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */