Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
MIPS: Introduce machinery for testing for MIPSxxR1/2. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
Ralf Baechle
and committed by
b4672d37
e7958bb9
+30
-5
arch/mips/kernel/cpu-probe.c
+30
-5
arch/mips/kernel/cpu-probe.c
···
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}
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}
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static char unknown_isa[] __initdata = KERN_ERR \
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"Unsupported ISA type, c0.config0: %d.";
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static inline unsigned int decode_config0(struct cpuinfo_mips *c)
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{
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unsigned int config0;
···
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isa = (config0 & MIPS_CONF_AT) >> 13;
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switch (isa) {
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case 0:
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c->isa_level = MIPS_CPU_ISA_M32R1;
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switch ((config0 >> 10) & 7) {
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case 0:
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c->isa_level = MIPS_CPU_ISA_M32R1;
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break;
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case 1:
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c->isa_level = MIPS_CPU_ISA_M32R2;
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break;
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default:
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goto unknown;
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}
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break;
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case 2:
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-
c->isa_level = MIPS_CPU_ISA_M64R1;
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switch ((config0 >> 10) & 7) {
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case 0:
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c->isa_level = MIPS_CPU_ISA_M64R1;
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break;
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case 1:
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c->isa_level = MIPS_CPU_ISA_M64R2;
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break;
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default:
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goto unknown;
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}
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break;
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default:
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panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
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goto unknown;
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}
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return config0 & MIPS_CONF_M;
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unknown:
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panic(unknown_isa, config0);
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}
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static inline unsigned int decode_config1(struct cpuinfo_mips *c)
···
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break;
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case PRID_IMP_34K:
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c->cputype = CPU_34K;
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c->isa_level = MIPS_CPU_ISA_M32R1;
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break;
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}
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}
···
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c->fpu_id = cpu_get_fpu_id();
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if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
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c->isa_level == MIPS_CPU_ISA_M64R1) {
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c->isa_level == MIPS_CPU_ISA_M32R2 ||
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c->isa_level == MIPS_CPU_ISA_M64R1 ||
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c->isa_level == MIPS_CPU_ISA_M64R2) {
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if (c->fpu_id & MIPS_FPIR_3D)
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c->ases |= MIPS_ASE_MIPS3D;
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}
+3
-3
arch/mips/kernel/time.c
+3
-3
arch/mips/kernel/time.c
···
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mips_hpt_init = c0_hpt_init;
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}
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-
if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32R1) ||
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(current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
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(current_cpu_data.isa_level == MIPS_CPU_ISA_II))
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if (cpu_has_mips32r1 || cpu_has_mips32r2 ||
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(current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
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(current_cpu_data.isa_level == MIPS_CPU_ISA_II))
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/*
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* We need to calibrate the counter but we don't have
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* 64-bit division.
+24
include/asm-mips/cpu-features.h
+24
include/asm-mips/cpu-features.h
···
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# ifndef cpu_has_64bit_addresses
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# define cpu_has_64bit_addresses 0
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# endif
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# ifndef cpu_has_mips32r1
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# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
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# endif
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# ifndef cpu_has_mips32r2
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# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
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# endif
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# ifndef cpu_has_mips64r1
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# define cpu_has_mips64r1 0
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# endif
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# ifndef cpu_has_mips64r2
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# define cpu_has_mips64r2 0
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# endif
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#endif
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#ifdef CONFIG_64BIT
···
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# endif
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# ifndef cpu_has_64bit_addresses
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# define cpu_has_64bit_addresses 1
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# endif
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# ifndef cpu_has_mips32r1
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# define cpu_has_mips32r1 0
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# endif
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# ifndef cpu_has_mips32r2
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# define cpu_has_mips32r2 0
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# endif
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# ifndef cpu_has_mips64r1
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# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
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# endif
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# ifndef cpu_has_mips64r2
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# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
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# endif
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#endif
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+3
-1
include/asm-mips/cpu.h
+3
-1
include/asm-mips/cpu.h
···
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#define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT)
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#define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT)
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#define MIPS_CPU_ISA_M32R1 0x00000020
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#define MIPS_CPU_ISA_M64R1 (0x00000040 | MIPS_CPU_ISA_64BIT)
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#define MIPS_CPU_ISA_M32R2 0x00000040
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#define MIPS_CPU_ISA_M64R1 (0x00000080 | MIPS_CPU_ISA_64BIT)
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#define MIPS_CPU_ISA_M64R2 (0x00000100 | MIPS_CPU_ISA_64BIT)
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/*
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* CPU Option encodings
+5
include/asm-mips/mach-ip22/cpu-feature-overrides.h
+5
include/asm-mips/mach-ip22/cpu-feature-overrides.h
+5
include/asm-mips/mach-ip27/cpu-feature-overrides.h
+5
include/asm-mips/mach-ip27/cpu-feature-overrides.h
+5
include/asm-mips/mach-ip32/cpu-feature-overrides.h
+5
include/asm-mips/mach-ip32/cpu-feature-overrides.h
+5
include/asm-mips/mach-ja/cpu-feature-overrides.h
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include/asm-mips/mach-ja/cpu-feature-overrides.h
+5
include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+5
include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+5
include/asm-mips/mach-rm200/cpu-feature-overrides.h
+5
include/asm-mips/mach-rm200/cpu-feature-overrides.h
···
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#define cpu_icache_line_size() 32
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#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */
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#define cpu_has_mips32r1 0
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#define cpu_has_mips32r2 0
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
+5
include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+5
include/asm-mips/mach-yosemite/cpu-feature-overrides.h