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drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine

With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS
registers for the 3rd DSC engine

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-6-ankit.k.nautiyal@intel.com

Ankit Nautiyal b3f5f0c8 3013e2e4

+11 -3
+5 -3
drivers/gpu/drm/i915/display/intel_vdsc.c
··· 402 402 403 403 pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder); 404 404 405 - if (dsc_reg_num >= 3) 405 + if (dsc_reg_num >= 4) 406 406 MISSING_CASE(dsc_reg_num); 407 + if (dsc_reg_num >= 3) 408 + dsc_reg[2] = BMG_DSC2_PPS(pipe, pps); 407 409 if (dsc_reg_num >= 2) 408 410 dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps); 409 411 if (dsc_reg_num >= 1) ··· 417 415 { 418 416 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 419 417 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 420 - i915_reg_t dsc_reg[2]; 418 + i915_reg_t dsc_reg[3]; 421 419 int i, vdsc_per_pipe, dsc_reg_num; 422 420 423 421 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); ··· 817 815 { 818 816 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 819 817 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 820 - i915_reg_t dsc_reg[2]; 818 + i915_reg_t dsc_reg[3]; 821 819 int i, vdsc_per_pipe, dsc_reg_num; 822 820 u32 val; 823 821
+6
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
··· 59 59 #define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) 60 60 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 61 61 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 62 + #define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB 0x78970 62 63 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 63 64 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 65 + #define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC 0x78A70 64 66 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 65 67 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 66 68 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) ··· 75 73 #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ 76 74 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 77 75 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 76 + #define _BMG_DSC2_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ 77 + _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB, \ 78 + _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC) 78 79 #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) 79 80 #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) 81 + #define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4)) 80 82 81 83 /* PPS 0 */ 82 84 #define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23)