Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

sfc: Cleanups in io.h

Most of the Falcon locking description does not apply to EF10.

Signed-off-by: Martin Habets <habetsm.xilinx@gmail.com>
Acked-by: Edward Cree <ecree.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Martin Habets and committed by
David S. Miller
b0d1fe9b ae9d445c

+9 -80
+9 -75
drivers/net/ethernet/sfc/io.h
··· 17 17 * 18 18 ************************************************************************** 19 19 * 20 - * Notes on locking strategy for the Falcon architecture: 20 + * The EF10 architecture exposes very few registers to the host and 21 + * most of them are only 32 bits wide. The only exceptions are the MC 22 + * doorbell register pair, which has its own latching, and 23 + * TX_DESC_UPD. 21 24 * 22 - * Many CSRs are very wide and cannot be read or written atomically. 23 - * Writes from the host are buffered by the Bus Interface Unit (BIU) 24 - * up to 128 bits. Whenever the host writes part of such a register, 25 - * the BIU collects the written value and does not write to the 26 - * underlying register until all 4 dwords have been written. A 27 - * similar buffering scheme applies to host access to the NIC's 64-bit 28 - * SRAM. 25 + * The TX_DESC_UPD DMA descriptor pointer is 128-bits but is a special 26 + * case in the BIU to avoid the need for locking in the host: 29 27 * 30 - * Writes to different CSRs and 64-bit SRAM words must be serialised, 31 - * since interleaved access can result in lost writes. We use 32 - * efx_nic::biu_lock for this. 33 - * 34 - * We also serialise reads from 128-bit CSRs and SRAM with the same 35 - * spinlock. This may not be necessary, but it doesn't really matter 36 - * as there are no such reads on the fast path. 37 - * 38 - * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 39 - * 128-bit but are special-cased in the BIU to avoid the need for 40 - * locking in the host: 41 - * 42 - * - They are write-only. 43 - * - The semantics of writing to these registers are such that 28 + * - It is write-only. 29 + * - The semantics of writing to this register is such that 44 30 * replacing the low 96 bits with zero does not affect functionality. 45 - * - If the host writes to the last dword address of such a register 31 + * - If the host writes to the last dword address of the register 46 32 * (i.e. the high 32 bits) the underlying register will always be 47 33 * written. If the collector and the current write together do not 48 34 * provide values for all 128 bits of the register, the low 96 bits 49 35 * will be written as zero. 50 - * - If the host writes to the address of any other part of such a 51 - * register while the collector already holds values for some other 52 - * register, the write is discarded and the collector maintains its 53 - * current state. 54 - * 55 - * The EF10 architecture exposes very few registers to the host and 56 - * most of them are only 32 bits wide. The only exceptions are the MC 57 - * doorbell register pair, which has its own latching, and 58 - * TX_DESC_UPD, which works in a similar way to the Falcon 59 - * architecture. 60 36 */ 61 37 62 38 #if BITS_PER_LONG == 64 ··· 101 125 spin_unlock_irqrestore(&efx->biu_lock, flags); 102 126 } 103 127 104 - /* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */ 105 - static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase, 106 - const efx_qword_t *value, unsigned int index) 107 - { 108 - unsigned int addr = index * sizeof(*value); 109 - unsigned long flags __attribute__ ((unused)); 110 - 111 - netif_vdbg(efx, hw, efx->net_dev, 112 - "writing SRAM address %x with " EFX_QWORD_FMT "\n", 113 - addr, EFX_QWORD_VAL(*value)); 114 - 115 - spin_lock_irqsave(&efx->biu_lock, flags); 116 - #ifdef EFX_USE_QWORD_IO 117 - __raw_writeq((__force u64)value->u64[0], membase + addr); 118 - #else 119 - __raw_writel((__force u32)value->u32[0], membase + addr); 120 - __raw_writel((__force u32)value->u32[1], membase + addr + 4); 121 - #endif 122 - spin_unlock_irqrestore(&efx->biu_lock, flags); 123 - } 124 - 125 128 /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */ 126 129 static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value, 127 130 unsigned int reg) ··· 129 174 netif_vdbg(efx, hw, efx->net_dev, 130 175 "read from register %x, got " EFX_OWORD_FMT "\n", reg, 131 176 EFX_OWORD_VAL(*value)); 132 - } 133 - 134 - /* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */ 135 - static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase, 136 - efx_qword_t *value, unsigned int index) 137 - { 138 - unsigned int addr = index * sizeof(*value); 139 - unsigned long flags __attribute__ ((unused)); 140 - 141 - spin_lock_irqsave(&efx->biu_lock, flags); 142 - #ifdef EFX_USE_QWORD_IO 143 - value->u64[0] = (__force __le64)__raw_readq(membase + addr); 144 - #else 145 - value->u32[0] = (__force __le32)__raw_readl(membase + addr); 146 - value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4); 147 - #endif 148 - spin_unlock_irqrestore(&efx->biu_lock, flags); 149 - 150 - netif_vdbg(efx, hw, efx->net_dev, 151 - "read from SRAM address %x, got "EFX_QWORD_FMT"\n", 152 - addr, EFX_QWORD_VAL(*value)); 153 177 } 154 178 155 179 /* Read a 32-bit CSR or SRAM */
-5
drivers/net/ethernet/sfc/nic.c
··· 272 272 case 4: /* 32-bit SRAM */ 273 273 efx_readd(efx, buf, table->offset + 4 * i); 274 274 break; 275 - case 8: /* 64-bit SRAM */ 276 - efx_sram_readq(efx, 277 - efx->membase + table->offset, 278 - buf, i); 279 - break; 280 275 case 16: /* 128-bit-readable register */ 281 276 efx_reado_table(efx, buf, table->offset, i); 282 277 break;