commit b08b69a110bd981909c248f89997dcdcdfd5a39c · tjh.dev/kernel

+38 -33

arch/arm/mach-s5p6442/include/mach/map.h

··· 1 1 /* linux/arch/arm/mach-s5p6442/include/mach/map.h 2 2 * 3 - * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 4 * http://www.samsung.com/ 5 5 * 6 6 * S5P6442 - Memory map definitions ··· 16 16 #include <plat/map-base.h> 17 17 #include <plat/map-s5p.h> 18 18 19 - #define S5P6442_PA_CHIPID (0xE0000000) 20 - #define S5P_PA_CHIPID S5P6442_PA_CHIPID 19 + #define S5P6442_PA_SDRAM 0x20000000 21 20 22 - #define S5P6442_PA_SYSCON (0xE0100000) 23 - #define S5P_PA_SYSCON S5P6442_PA_SYSCON 21 + #define S5P6442_PA_I2S0 0xC0B00000 22 + #define S5P6442_PA_I2S1 0xF2200000 24 23 25 - #define S5P6442_PA_GPIO (0xE0200000) 24 + #define S5P6442_PA_CHIPID 0xE0000000 26 25 27 - #define S5P6442_PA_VIC0 (0xE4000000) 28 - #define S5P6442_PA_VIC1 (0xE4100000) 29 - #define S5P6442_PA_VIC2 (0xE4200000) 26 + #define S5P6442_PA_SYSCON 0xE0100000 30 27 31 - #define S5P6442_PA_SROMC (0xE7000000) 32 - #define S5P_PA_SROMC S5P6442_PA_SROMC 28 + #define S5P6442_PA_GPIO 0xE0200000 29 + 30 + #define S5P6442_PA_VIC0 0xE4000000 31 + #define S5P6442_PA_VIC1 0xE4100000 32 + #define S5P6442_PA_VIC2 0xE4200000 33 + 34 + #define S5P6442_PA_SROMC 0xE7000000 33 35 34 36 #define S5P6442_PA_MDMA 0xE8000000 35 37 #define S5P6442_PA_PDMA 0xE9000000 36 38 37 - #define S5P6442_PA_TIMER (0xEA000000) 38 - #define S5P_PA_TIMER S5P6442_PA_TIMER 39 + #define S5P6442_PA_TIMER 0xEA000000 39 40 40 - #define S5P6442_PA_SYSTIMER (0xEA100000) 41 + #define S5P6442_PA_SYSTIMER 0xEA100000 41 42 42 - #define S5P6442_PA_WATCHDOG (0xEA200000) 43 + #define S5P6442_PA_WATCHDOG 0xEA200000 43 44 44 - #define S5P6442_PA_UART (0xEC000000) 45 + #define S5P6442_PA_UART 0xEC000000 45 46 46 - #define S5P_PA_UART0 (S5P6442_PA_UART + 0x0) 47 - #define S5P_PA_UART1 (S5P6442_PA_UART + 0x400) 48 - #define S5P_PA_UART2 (S5P6442_PA_UART + 0x800) 49 - #define S5P_SZ_UART SZ_256 50 - 51 - #define S5P6442_PA_IIC0 (0xEC100000) 52 - 53 - #define S5P6442_PA_SDRAM (0x20000000) 54 - #define S5P_PA_SDRAM S5P6442_PA_SDRAM 47 + #define S5P6442_PA_IIC0 0xEC100000 55 48 56 49 #define S5P6442_PA_SPI 0xEC300000 57 50 58 - /* I2S */ 59 - #define S5P6442_PA_I2S0 0xC0B00000 60 - #define S5P6442_PA_I2S1 0xF2200000 61 - 62 - /* PCM */ 63 51 #define S5P6442_PA_PCM0 0xF2400000 64 52 #define S5P6442_PA_PCM1 0xF2500000 65 53 66 - /* compatibiltiy defines. */ 67 - #define S3C_PA_WDT S5P6442_PA_WATCHDOG 68 - #define S3C_PA_UART S5P6442_PA_UART 54 + /* Compatibiltiy Defines */ 55 + 69 56 #define S3C_PA_IIC S5P6442_PA_IIC0 57 + #define S3C_PA_WDT S5P6442_PA_WATCHDOG 58 + 59 + #define S5P_PA_CHIPID S5P6442_PA_CHIPID 60 + #define S5P_PA_SDRAM S5P6442_PA_SDRAM 61 + #define S5P_PA_SROMC S5P6442_PA_SROMC 62 + #define S5P_PA_SYSCON S5P6442_PA_SYSCON 63 + #define S5P_PA_TIMER S5P6442_PA_TIMER 64 + 65 + /* UART */ 66 + 67 + #define S3C_PA_UART S5P6442_PA_UART 68 + 69 + #define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) 70 + #define S5P_PA_UART0 S5P_PA_UART(0) 71 + #define S5P_PA_UART1 S5P_PA_UART(1) 72 + #define S5P_PA_UART2 S5P_PA_UART(2) 73 + 74 + #define S5P_SZ_UART SZ_256 70 75 71 76 #endif /* __ASM_ARCH_MAP_H */

+52 -51

arch/arm/mach-s5p64x0/include/mach/map.h

··· 1 1 /* linux/arch/arm/mach-s5p64x0/include/mach/map.h 2 2 * 3 - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 3 + * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. 4 4 * http://www.samsung.com 5 5 * 6 6 * S5P64X0 - Memory map definitions ··· 16 16 #include <plat/map-base.h> 17 17 #include <plat/map-s5p.h> 18 18 19 - #define S5P64X0_PA_SDRAM (0x20000000) 19 + #define S5P64X0_PA_SDRAM 0x20000000 20 20 21 - #define S5P64X0_PA_CHIPID (0xE0000000) 21 + #define S5P64X0_PA_CHIPID 0xE0000000 22 + 23 + #define S5P64X0_PA_SYSCON 0xE0100000 24 + 25 + #define S5P64X0_PA_GPIO 0xE0308000 26 + 27 + #define S5P64X0_PA_VIC0 0xE4000000 28 + #define S5P64X0_PA_VIC1 0xE4100000 29 + 30 + #define S5P64X0_PA_SROMC 0xE7000000 31 + 32 + #define S5P64X0_PA_PDMA 0xE9000000 33 + 34 + #define S5P64X0_PA_TIMER 0xEA000000 35 + #define S5P64X0_PA_RTC 0xEA100000 36 + #define S5P64X0_PA_WDT 0xEA200000 37 + 38 + #define S5P6440_PA_IIC0 0xEC104000 39 + #define S5P6440_PA_IIC1 0xEC20F000 40 + #define S5P6450_PA_IIC0 0xEC100000 41 + #define S5P6450_PA_IIC1 0xEC200000 42 + 43 + #define S5P64X0_PA_SPI0 0xEC400000 44 + #define S5P64X0_PA_SPI1 0xEC500000 45 + 46 + #define S5P64X0_PA_HSOTG 0xED100000 47 + 48 + #define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 49 + 50 + #define S5P64X0_PA_I2S 0xF2000000 51 + #define S5P6450_PA_I2S1 0xF2800000 52 + #define S5P6450_PA_I2S2 0xF2900000 53 + 54 + #define S5P64X0_PA_PCM 0xF2100000 55 + 56 + #define S5P64X0_PA_ADC 0xF3000000 57 + 58 + /* Compatibiltiy Defines */ 59 + 60 + #define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0) 61 + #define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1) 62 + #define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2) 63 + #define S3C_PA_IIC S5P6440_PA_IIC0 64 + #define S3C_PA_IIC1 S5P6440_PA_IIC1 65 + #define S3C_PA_RTC S5P64X0_PA_RTC 66 + #define S3C_PA_WDT S5P64X0_PA_WDT 67 + 22 68 #define S5P_PA_CHIPID S5P64X0_PA_CHIPID 23 - 24 - #define S5P64X0_PA_SYSCON (0xE0100000) 25 - #define S5P_PA_SYSCON S5P64X0_PA_SYSCON 26 - 27 - #define S5P64X0_PA_GPIO (0xE0308000) 28 - 29 - #define S5P64X0_PA_VIC0 (0xE4000000) 30 - #define S5P64X0_PA_VIC1 (0xE4100000) 31 - 32 - #define S5P64X0_PA_SROMC (0xE7000000) 33 69 #define S5P_PA_SROMC S5P64X0_PA_SROMC 34 - 35 - #define S5P64X0_PA_PDMA (0xE9000000) 36 - 37 - #define S5P64X0_PA_TIMER (0xEA000000) 70 + #define S5P_PA_SYSCON S5P64X0_PA_SYSCON 38 71 #define S5P_PA_TIMER S5P64X0_PA_TIMER 39 72 40 - #define S5P64X0_PA_RTC (0xEA100000) 73 + #define SAMSUNG_PA_ADC S5P64X0_PA_ADC 41 74 42 - #define S5P64X0_PA_WDT (0xEA200000) 75 + /* UART */ 43 76 44 77 #define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET)) 45 78 #define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000)) ··· 85 52 #define S5P_PA_UART5 S5P6450_PA_UART(5) 86 53 87 54 #define S5P_SZ_UART SZ_256 88 - 89 - #define S5P6440_PA_IIC0 (0xEC104000) 90 - #define S5P6440_PA_IIC1 (0xEC20F000) 91 - #define S5P6450_PA_IIC0 (0xEC100000) 92 - #define S5P6450_PA_IIC1 (0xEC200000) 93 - 94 - #define S5P64X0_PA_SPI0 (0xEC400000) 95 - #define S5P64X0_PA_SPI1 (0xEC500000) 96 - 97 - #define S5P64X0_PA_HSOTG (0xED100000) 98 - 99 - #define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 100 - 101 - #define S5P64X0_PA_I2S (0xF2000000) 102 - #define S5P6450_PA_I2S1 0xF2800000 103 - #define S5P6450_PA_I2S2 0xF2900000 104 - 105 - #define S5P64X0_PA_PCM (0xF2100000) 106 - 107 - #define S5P64X0_PA_ADC (0xF3000000) 108 - 109 - /* compatibiltiy defines. */ 110 - 111 - #define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0) 112 - #define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1) 113 - #define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2) 114 - #define S3C_PA_IIC S5P6440_PA_IIC0 115 - #define S3C_PA_IIC1 S5P6440_PA_IIC1 116 - #define S3C_PA_RTC S5P64X0_PA_RTC 117 - #define S3C_PA_WDT S5P64X0_PA_WDT 118 - 119 - #define SAMSUNG_PA_ADC S5P64X0_PA_ADC 120 55 121 56 #endif /* __ASM_ARCH_MAP_H */

+82 -109

arch/arm/mach-s5pc100/include/mach/map.h

··· 1 1 /* linux/arch/arm/mach-s5pc100/include/mach/map.h 2 2 * 3 + * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 + * http://www.samsung.com/ 5 + * 3 6 * Copyright 2009 Samsung Electronics Co. 4 7 * Byungho Min <bhmin@samsung.com> 5 8 * ··· 19 16 #include <plat/map-base.h> 20 17 #include <plat/map-s5p.h> 21 18 22 - /* 23 - * map-base.h has already defined virtual memory address 24 - * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s) 25 - * S3C_VA_SYS S3C_ADDR(0x00100000) system control 26 - * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used) 27 - * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block 28 - * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog 29 - * S3C_VA_UART S3C_ADDR(0x01000000) UART 30 - * 31 - * S5PC100 specific virtual memory address can be defined here 32 - * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO 33 - * 34 - */ 19 + #define S5PC100_PA_SDRAM 0x20000000 35 20 36 - #define S5PC100_PA_ONENAND_BUF (0xB0000000) 37 - #define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M) 21 + #define S5PC100_PA_ONENAND 0xE7100000 22 + #define S5PC100_PA_ONENAND_BUF 0xB0000000 38 23 39 - /* Chip ID */ 24 + #define S5PC100_PA_CHIPID 0xE0000000 40 25 41 - #define S5PC100_PA_CHIPID (0xE0000000) 42 - #define S5P_PA_CHIPID S5PC100_PA_CHIPID 26 + #define S5PC100_PA_SYSCON 0xE0100000 43 27 44 - #define S5PC100_PA_SYSCON (0xE0100000) 45 - #define S5P_PA_SYSCON S5PC100_PA_SYSCON 28 + #define S5PC100_PA_OTHERS 0xE0200000 46 29 47 - #define S5PC100_PA_OTHERS (0xE0200000) 48 - #define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) 30 + #define S5PC100_PA_GPIO 0xE0300000 49 31 50 - #define S5PC100_PA_GPIO (0xE0300000) 51 - #define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) 32 + #define S5PC100_PA_VIC0 0xE4000000 33 + #define S5PC100_PA_VIC1 0xE4100000 34 + #define S5PC100_PA_VIC2 0xE4200000 52 35 53 - /* Interrupt */ 54 - #define S5PC100_PA_VIC0 (0xE4000000) 55 - #define S5PC100_PA_VIC1 (0xE4100000) 56 - #define S5PC100_PA_VIC2 (0xE4200000) 57 - #define S5PC100_VA_VIC S3C_VA_IRQ 58 - #define S5PC100_VA_VIC_OFFSET 0x10000 59 - #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) 36 + #define S5PC100_PA_SROMC 0xE7000000 60 37 61 - #define S5PC100_PA_SROMC (0xE7000000) 62 - #define S5P_PA_SROMC S5PC100_PA_SROMC 38 + #define S5PC100_PA_CFCON 0xE7800000 63 39 64 - #define S5PC100_PA_ONENAND (0xE7100000) 40 + #define S5PC100_PA_MDMA 0xE8100000 41 + #define S5PC100_PA_PDMA0 0xE9000000 42 + #define S5PC100_PA_PDMA1 0xE9200000 65 43 66 - #define S5PC100_PA_CFCON (0xE7800000) 44 + #define S5PC100_PA_TIMER 0xEA000000 45 + #define S5PC100_PA_SYSTIMER 0xEA100000 46 + #define S5PC100_PA_WATCHDOG 0xEA200000 47 + #define S5PC100_PA_RTC 0xEA300000 67 48 68 - /* DMA */ 69 - #define S5PC100_PA_MDMA (0xE8100000) 70 - #define S5PC100_PA_PDMA0 (0xE9000000) 71 - #define S5PC100_PA_PDMA1 (0xE9200000) 49 + #define S5PC100_PA_UART 0xEC000000 72 50 73 - /* Timer */ 74 - #define S5PC100_PA_TIMER (0xEA000000) 75 - #define S5P_PA_TIMER S5PC100_PA_TIMER 51 + #define S5PC100_PA_IIC0 0xEC100000 52 + #define S5PC100_PA_IIC1 0xEC200000 76 53 77 - #define S5PC100_PA_SYSTIMER (0xEA100000) 54 + #define S5PC100_PA_SPI0 0xEC300000 55 + #define S5PC100_PA_SPI1 0xEC400000 56 + #define S5PC100_PA_SPI2 0xEC500000 78 57 79 - #define S5PC100_PA_WATCHDOG (0xEA200000) 80 - #define S5PC100_PA_RTC (0xEA300000) 58 + #define S5PC100_PA_USB_HSOTG 0xED200000 59 + #define S5PC100_PA_USB_HSPHY 0xED300000 81 60 82 - #define S5PC100_PA_UART (0xEC000000) 61 + #define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 83 62 84 - #define S5P_PA_UART0 (S5PC100_PA_UART + 0x0) 85 - #define S5P_PA_UART1 (S5PC100_PA_UART + 0x400) 86 - #define S5P_PA_UART2 (S5PC100_PA_UART + 0x800) 87 - #define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00) 88 - #define S5P_SZ_UART SZ_256 63 + #define S5PC100_PA_FB 0xEE000000 89 64 90 - #define S5PC100_PA_IIC0 (0xEC100000) 91 - #define S5PC100_PA_IIC1 (0xEC200000) 65 + #define S5PC100_PA_FIMC0 0xEE200000 66 + #define S5PC100_PA_FIMC1 0xEE300000 67 + #define S5PC100_PA_FIMC2 0xEE400000 92 68 93 - /* SPI */ 94 - #define S5PC100_PA_SPI0 0xEC300000 95 - #define S5PC100_PA_SPI1 0xEC400000 96 - #define S5PC100_PA_SPI2 0xEC500000 69 + #define S5PC100_PA_I2S0 0xF2000000 70 + #define S5PC100_PA_I2S1 0xF2100000 71 + #define S5PC100_PA_I2S2 0xF2200000 97 72 98 - /* USB HS OTG */ 99 - #define S5PC100_PA_USB_HSOTG (0xED200000) 100 - #define S5PC100_PA_USB_HSPHY (0xED300000) 73 + #define S5PC100_PA_AC97 0xF2300000 101 74 102 - #define S5PC100_PA_FB (0xEE000000) 75 + #define S5PC100_PA_PCM0 0xF2400000 76 + #define S5PC100_PA_PCM1 0xF2500000 103 77 104 - #define S5PC100_PA_FIMC0 (0xEE200000) 105 - #define S5PC100_PA_FIMC1 (0xEE300000) 106 - #define S5PC100_PA_FIMC2 (0xEE400000) 78 + #define S5PC100_PA_SPDIF 0xF2600000 107 79 108 - #define S5PC100_PA_I2S0 (0xF2000000) 109 - #define S5PC100_PA_I2S1 (0xF2100000) 110 - #define S5PC100_PA_I2S2 (0xF2200000) 80 + #define S5PC100_PA_TSADC 0xF3000000 111 81 112 - #define S5PC100_PA_AC97 0xF2300000 82 + #define S5PC100_PA_KEYPAD 0xF3100000 113 83 114 - /* PCM */ 115 - #define S5PC100_PA_PCM0 0xF2400000 116 - #define S5PC100_PA_PCM1 0xF2500000 84 + /* Compatibiltiy Defines */ 117 85 118 - #define S5PC100_PA_SPDIF 0xF2600000 86 + #define S3C_PA_FB S5PC100_PA_FB 87 + #define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0) 88 + #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) 89 + #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) 90 + #define S3C_PA_IIC S5PC100_PA_IIC0 91 + #define S3C_PA_IIC1 S5PC100_PA_IIC1 92 + #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD 93 + #define S3C_PA_ONENAND S5PC100_PA_ONENAND 94 + #define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF 95 + #define S3C_PA_RTC S5PC100_PA_RTC 96 + #define S3C_PA_TSADC S5PC100_PA_TSADC 97 + #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG 98 + #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY 99 + #define S3C_PA_WDT S5PC100_PA_WATCHDOG 119 100 120 - #define S5PC100_PA_TSADC (0xF3000000) 101 + #define S5P_PA_CHIPID S5PC100_PA_CHIPID 102 + #define S5P_PA_FIMC0 S5PC100_PA_FIMC0 103 + #define S5P_PA_FIMC1 S5PC100_PA_FIMC1 104 + #define S5P_PA_FIMC2 S5PC100_PA_FIMC2 105 + #define S5P_PA_SDRAM S5PC100_PA_SDRAM 106 + #define S5P_PA_SROMC S5PC100_PA_SROMC 107 + #define S5P_PA_SYSCON S5PC100_PA_SYSCON 108 + #define S5P_PA_TIMER S5PC100_PA_TIMER 121 109 122 - /* KEYPAD */ 123 - #define S5PC100_PA_KEYPAD (0xF3100000) 110 + #define SAMSUNG_PA_ADC S5PC100_PA_TSADC 111 + #define SAMSUNG_PA_CFCON S5PC100_PA_CFCON 112 + #define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD 124 113 125 - #define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 114 + #define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) 126 115 127 - #define S5PC100_PA_SDRAM (0x20000000) 128 - #define S5P_PA_SDRAM S5PC100_PA_SDRAM 116 + #define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M) 129 117 130 - /* compatibiltiy defines. */ 131 - #define S3C_PA_UART S5PC100_PA_UART 132 - #define S3C_PA_IIC S5PC100_PA_IIC0 133 - #define S3C_PA_IIC1 S5PC100_PA_IIC1 134 - #define S3C_PA_FB S5PC100_PA_FB 135 - #define S3C_PA_G2D S5PC100_PA_G2D 136 - #define S3C_PA_G3D S5PC100_PA_G3D 137 - #define S3C_PA_JPEG S5PC100_PA_JPEG 138 - #define S3C_PA_ROTATOR S5PC100_PA_ROTATOR 139 - #define S5P_VA_VIC0 S5PC1XX_VA_VIC(0) 140 - #define S5P_VA_VIC1 S5PC1XX_VA_VIC(1) 141 - #define S5P_VA_VIC2 S5PC1XX_VA_VIC(2) 142 - #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG 143 - #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY 144 - #define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0) 145 - #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) 146 - #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) 147 - #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD 148 - #define S3C_PA_WDT S5PC100_PA_WATCHDOG 149 - #define S3C_PA_TSADC S5PC100_PA_TSADC 150 - #define S3C_PA_ONENAND S5PC100_PA_ONENAND 151 - #define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF 152 - #define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF 153 - #define S3C_PA_RTC S5PC100_PA_RTC 118 + /* UART */ 154 119 155 - #define SAMSUNG_PA_ADC S5PC100_PA_TSADC 156 - #define SAMSUNG_PA_CFCON S5PC100_PA_CFCON 157 - #define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD 120 + #define S3C_PA_UART S5PC100_PA_UART 158 121 159 - #define S5P_PA_FIMC0 S5PC100_PA_FIMC0 160 - #define S5P_PA_FIMC1 S5PC100_PA_FIMC1 161 - #define S5P_PA_FIMC2 S5PC100_PA_FIMC2 122 + #define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) 123 + #define S5P_PA_UART0 S5P_PA_UART(0) 124 + #define S5P_PA_UART1 S5P_PA_UART(1) 125 + #define S5P_PA_UART2 S5P_PA_UART(2) 126 + #define S5P_PA_UART3 S5P_PA_UART(3) 162 127 163 - #endif /* __ASM_ARCH_C100_MAP_H */ 128 + #define S5P_SZ_UART SZ_256 129 + 130 + #endif /* __ASM_ARCH_MAP_H */

+83 -85

arch/arm/mach-s5pv210/include/mach/map.h

··· 1 1 /* linux/arch/arm/mach-s5pv210/include/mach/map.h 2 2 * 3 - * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 4 * http://www.samsung.com/ 5 5 * 6 6 * S5PV210 - Memory map definitions ··· 16 16 #include <plat/map-base.h> 17 17 #include <plat/map-s5p.h> 18 18 19 - #define S5PV210_PA_SROM_BANK5 (0xA8000000) 19 + #define S5PV210_PA_SDRAM 0x20000000 20 20 21 - #define S5PC110_PA_ONENAND (0xB0000000) 22 - #define S5P_PA_ONENAND S5PC110_PA_ONENAND 21 + #define S5PV210_PA_SROM_BANK5 0xA8000000 23 22 24 - #define S5PC110_PA_ONENAND_DMA (0xB0600000) 25 - #define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA 23 + #define S5PC110_PA_ONENAND 0xB0000000 24 + #define S5PC110_PA_ONENAND_DMA 0xB0600000 26 25 27 - #define S5PV210_PA_CHIPID (0xE0000000) 28 - #define S5P_PA_CHIPID S5PV210_PA_CHIPID 26 + #define S5PV210_PA_CHIPID 0xE0000000 29 27 30 - #define S5PV210_PA_SYSCON (0xE0100000) 31 - #define S5P_PA_SYSCON S5PV210_PA_SYSCON 28 + #define S5PV210_PA_SYSCON 0xE0100000 32 29 33 - #define S5PV210_PA_GPIO (0xE0200000) 30 + #define S5PV210_PA_GPIO 0xE0200000 34 31 35 - /* SPI */ 36 - #define S5PV210_PA_SPI0 0xE1300000 37 - #define S5PV210_PA_SPI1 0xE1400000 32 + #define S5PV210_PA_SPDIF 0xE1100000 38 33 39 - #define S5PV210_PA_KEYPAD (0xE1600000) 34 + #define S5PV210_PA_SPI0 0xE1300000 35 + #define S5PV210_PA_SPI1 0xE1400000 40 36 41 - #define S5PV210_PA_IIC0 (0xE1800000) 42 - #define S5PV210_PA_IIC1 (0xFAB00000) 43 - #define S5PV210_PA_IIC2 (0xE1A00000) 37 + #define S5PV210_PA_KEYPAD 0xE1600000 44 38 45 - #define S5PV210_PA_TIMER (0xE2500000) 46 - #define S5P_PA_TIMER S5PV210_PA_TIMER 39 + #define S5PV210_PA_ADC 0xE1700000 47 40 48 - #define S5PV210_PA_SYSTIMER (0xE2600000) 41 + #define S5PV210_PA_IIC0 0xE1800000 42 + #define S5PV210_PA_IIC1 0xFAB00000 43 + #define S5PV210_PA_IIC2 0xE1A00000 49 44 50 - #define S5PV210_PA_WATCHDOG (0xE2700000) 45 + #define S5PV210_PA_AC97 0xE2200000 51 46 52 - #define S5PV210_PA_RTC (0xE2800000) 53 - #define S5PV210_PA_UART (0xE2900000) 47 + #define S5PV210_PA_PCM0 0xE2300000 48 + #define S5PV210_PA_PCM1 0xE1200000 49 + #define S5PV210_PA_PCM2 0xE2B00000 54 50 55 - #define S5P_PA_UART0 (S5PV210_PA_UART + 0x0) 56 - #define S5P_PA_UART1 (S5PV210_PA_UART + 0x400) 57 - #define S5P_PA_UART2 (S5PV210_PA_UART + 0x800) 58 - #define S5P_PA_UART3 (S5PV210_PA_UART + 0xC00) 51 + #define S5PV210_PA_TIMER 0xE2500000 52 + #define S5PV210_PA_SYSTIMER 0xE2600000 53 + #define S5PV210_PA_WATCHDOG 0xE2700000 54 + #define S5PV210_PA_RTC 0xE2800000 59 55 60 - #define S5P_SZ_UART SZ_256 56 + #define S5PV210_PA_UART 0xE2900000 61 57 62 - #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 58 + #define S5PV210_PA_SROMC 0xE8000000 63 59 64 - #define S5PV210_PA_SROMC (0xE8000000) 65 - #define S5P_PA_SROMC S5PV210_PA_SROMC 60 + #define S5PV210_PA_CFCON 0xE8200000 66 61 67 - #define S5PV210_PA_CFCON (0xE8200000) 62 + #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) 68 63 69 - #define S5PV210_PA_MDMA 0xFA200000 70 - #define S5PV210_PA_PDMA0 0xE0900000 71 - #define S5PV210_PA_PDMA1 0xE0A00000 64 + #define S5PV210_PA_HSOTG 0xEC000000 65 + #define S5PV210_PA_HSPHY 0xEC100000 72 66 73 - #define S5PV210_PA_FB (0xF8000000) 67 + #define S5PV210_PA_IIS0 0xEEE30000 68 + #define S5PV210_PA_IIS1 0xE2100000 69 + #define S5PV210_PA_IIS2 0xE2A00000 74 70 75 - #define S5PV210_PA_FIMC0 (0xFB200000) 76 - #define S5PV210_PA_FIMC1 (0xFB300000) 77 - #define S5PV210_PA_FIMC2 (0xFB400000) 71 + #define S5PV210_PA_DMC0 0xF0000000 72 + #define S5PV210_PA_DMC1 0xF1400000 78 73 79 - #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) 74 + #define S5PV210_PA_VIC0 0xF2000000 75 + #define S5PV210_PA_VIC1 0xF2100000 76 + #define S5PV210_PA_VIC2 0xF2200000 77 + #define S5PV210_PA_VIC3 0xF2300000 80 78 81 - #define S5PV210_PA_HSOTG (0xEC000000) 82 - #define S5PV210_PA_HSPHY (0xEC100000) 79 + #define S5PV210_PA_FB 0xF8000000 83 80 84 - #define S5PV210_PA_VIC0 (0xF2000000) 85 - #define S5PV210_PA_VIC1 (0xF2100000) 86 - #define S5PV210_PA_VIC2 (0xF2200000) 87 - #define S5PV210_PA_VIC3 (0xF2300000) 81 + #define S5PV210_PA_MDMA 0xFA200000 82 + #define S5PV210_PA_PDMA0 0xE0900000 83 + #define S5PV210_PA_PDMA1 0xE0A00000 88 84 89 - #define S5PV210_PA_SDRAM (0x20000000) 90 - #define S5P_PA_SDRAM S5PV210_PA_SDRAM 85 + #define S5PV210_PA_MIPI_CSIS 0xFA600000 91 86 92 - /* S/PDIF */ 93 - #define S5PV210_PA_SPDIF 0xE1100000 87 + #define S5PV210_PA_FIMC0 0xFB200000 88 + #define S5PV210_PA_FIMC1 0xFB300000 89 + #define S5PV210_PA_FIMC2 0xFB400000 94 90 95 - /* I2S */ 96 - #define S5PV210_PA_IIS0 0xEEE30000 97 - #define S5PV210_PA_IIS1 0xE2100000 98 - #define S5PV210_PA_IIS2 0xE2A00000 91 + /* Compatibiltiy Defines */ 99 92 100 - /* PCM */ 101 - #define S5PV210_PA_PCM0 0xE2300000 102 - #define S5PV210_PA_PCM1 0xE1200000 103 - #define S5PV210_PA_PCM2 0xE2B00000 93 + #define S3C_PA_FB S5PV210_PA_FB 94 + #define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) 95 + #define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1) 96 + #define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2) 97 + #define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3) 98 + #define S3C_PA_IIC S5PV210_PA_IIC0 99 + #define S3C_PA_IIC1 S5PV210_PA_IIC1 100 + #define S3C_PA_IIC2 S5PV210_PA_IIC2 101 + #define S3C_PA_RTC S5PV210_PA_RTC 102 + #define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG 103 + #define S3C_PA_WDT S5PV210_PA_WATCHDOG 104 104 105 - /* AC97 */ 106 - #define S5PV210_PA_AC97 0xE2200000 105 + #define S5P_PA_CHIPID S5PV210_PA_CHIPID 106 + #define S5P_PA_FIMC0 S5PV210_PA_FIMC0 107 + #define S5P_PA_FIMC1 S5PV210_PA_FIMC1 108 + #define S5P_PA_FIMC2 S5PV210_PA_FIMC2 109 + #define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS 110 + #define S5P_PA_ONENAND S5PC110_PA_ONENAND 111 + #define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA 112 + #define S5P_PA_SDRAM S5PV210_PA_SDRAM 113 + #define S5P_PA_SROMC S5PV210_PA_SROMC 114 + #define S5P_PA_SYSCON S5PV210_PA_SYSCON 115 + #define S5P_PA_TIMER S5PV210_PA_TIMER 107 116 108 - #define S5PV210_PA_ADC (0xE1700000) 117 + #define SAMSUNG_PA_ADC S5PV210_PA_ADC 118 + #define SAMSUNG_PA_CFCON S5PV210_PA_CFCON 119 + #define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD 109 120 110 - #define S5PV210_PA_DMC0 (0xF0000000) 111 - #define S5PV210_PA_DMC1 (0xF1400000) 121 + /* UART */ 112 122 113 - #define S5PV210_PA_MIPI_CSIS 0xFA600000 123 + #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 114 124 115 - /* compatibiltiy defines. */ 116 - #define S3C_PA_UART S5PV210_PA_UART 117 - #define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) 118 - #define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1) 119 - #define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2) 120 - #define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3) 121 - #define S3C_PA_IIC S5PV210_PA_IIC0 122 - #define S3C_PA_IIC1 S5PV210_PA_IIC1 123 - #define S3C_PA_IIC2 S5PV210_PA_IIC2 124 - #define S3C_PA_FB S5PV210_PA_FB 125 - #define S3C_PA_RTC S5PV210_PA_RTC 126 - #define S3C_PA_WDT S5PV210_PA_WATCHDOG 127 - #define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG 128 - #define S5P_PA_FIMC0 S5PV210_PA_FIMC0 129 - #define S5P_PA_FIMC1 S5PV210_PA_FIMC1 130 - #define S5P_PA_FIMC2 S5PV210_PA_FIMC2 131 - #define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS 125 + #define S3C_PA_UART S5PV210_PA_UART 132 126 133 - #define SAMSUNG_PA_ADC S5PV210_PA_ADC 134 - #define SAMSUNG_PA_CFCON S5PV210_PA_CFCON 135 - #define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD 127 + #define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) 128 + #define S5P_PA_UART0 S5P_PA_UART(0) 129 + #define S5P_PA_UART1 S5P_PA_UART(1) 130 + #define S5P_PA_UART2 S5P_PA_UART(2) 131 + #define S5P_PA_UART3 S5P_PA_UART(3) 132 + 133 + #define S5P_SZ_UART SZ_256 136 134 137 135 #endif /* __ASM_ARCH_MAP_H */

+9 -6

arch/arm/mach-s5pv210/mach-aquila.c

··· 149 149 150 150 static struct regulator_init_data aquila_ldo3_data = { 151 151 .constraints = { 152 - .name = "VUSB/MIPI_1.1V", 152 + .name = "VUSB+MIPI_1.1V", 153 153 .min_uV = 1100000, 154 154 .max_uV = 1100000, 155 155 .apply_uV = 1, ··· 197 197 198 198 static struct regulator_init_data aquila_ldo8_data = { 199 199 .constraints = { 200 - .name = "VUSB/VADC_3.3V", 200 + .name = "VUSB+VADC_3.3V", 201 201 .min_uV = 3300000, 202 202 .max_uV = 3300000, 203 203 .apply_uV = 1, ··· 207 207 208 208 static struct regulator_init_data aquila_ldo9_data = { 209 209 .constraints = { 210 - .name = "VCC/VCAM_2.8V", 210 + .name = "VCC+VCAM_2.8V", 211 211 .min_uV = 2800000, 212 212 .max_uV = 2800000, 213 213 .apply_uV = 1, ··· 381 381 .buck1_set1 = S5PV210_GPH0(3), 382 382 .buck1_set2 = S5PV210_GPH0(4), 383 383 .buck2_set3 = S5PV210_GPH0(5), 384 - .buck1_max_voltage1 = 1200000, 385 - .buck1_max_voltage2 = 1200000, 386 - .buck2_max_voltage = 1200000, 384 + .buck1_voltage1 = 1200000, 385 + .buck1_voltage2 = 1200000, 386 + .buck1_voltage3 = 1200000, 387 + .buck1_voltage4 = 1200000, 388 + .buck2_voltage1 = 1200000, 389 + .buck2_voltage2 = 1200000, 387 390 }; 388 391 #endif 389 392

+9 -6

arch/arm/mach-s5pv210/mach-goni.c

··· 288 288 289 289 static struct regulator_init_data goni_ldo3_data = { 290 290 .constraints = { 291 - .name = "VUSB/MIPI_1.1V", 291 + .name = "VUSB+MIPI_1.1V", 292 292 .min_uV = 1100000, 293 293 .max_uV = 1100000, 294 294 .apply_uV = 1, ··· 337 337 338 338 static struct regulator_init_data goni_ldo8_data = { 339 339 .constraints = { 340 - .name = "VUSB/VADC_3.3V", 340 + .name = "VUSB+VADC_3.3V", 341 341 .min_uV = 3300000, 342 342 .max_uV = 3300000, 343 343 .apply_uV = 1, ··· 347 347 348 348 static struct regulator_init_data goni_ldo9_data = { 349 349 .constraints = { 350 - .name = "VCC/VCAM_2.8V", 350 + .name = "VCC+VCAM_2.8V", 351 351 .min_uV = 2800000, 352 352 .max_uV = 2800000, 353 353 .apply_uV = 1, ··· 521 521 .buck1_set1 = S5PV210_GPH0(3), 522 522 .buck1_set2 = S5PV210_GPH0(4), 523 523 .buck2_set3 = S5PV210_GPH0(5), 524 - .buck1_max_voltage1 = 1200000, 525 - .buck1_max_voltage2 = 1200000, 526 - .buck2_max_voltage = 1200000, 524 + .buck1_voltage1 = 1200000, 525 + .buck1_voltage2 = 1200000, 526 + .buck1_voltage3 = 1200000, 527 + .buck1_voltage4 = 1200000, 528 + .buck2_voltage1 = 1200000, 529 + .buck2_voltage2 = 1200000, 527 530 }; 528 531 #endif 529 532

+74 -77

arch/arm/mach-s5pv310/include/mach/map.h

··· 1 1 /* linux/arch/arm/mach-s5pv310/include/mach/map.h 2 2 * 3 - * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 4 * http://www.samsung.com/ 5 5 * 6 6 * S5PV310 - Memory map definitions ··· 23 23 24 24 #include <plat/map-s5p.h> 25 25 26 - #define S5PV310_PA_SYSRAM (0x02025000) 26 + #define S5PV310_PA_SYSRAM 0x02025000 27 + 28 + #define S5PV310_PA_I2S0 0x03830000 29 + #define S5PV310_PA_I2S1 0xE3100000 30 + #define S5PV310_PA_I2S2 0xE2A00000 31 + 32 + #define S5PV310_PA_PCM0 0x03840000 33 + #define S5PV310_PA_PCM1 0x13980000 34 + #define S5PV310_PA_PCM2 0x13990000 27 35 28 36 #define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) 29 37 30 - #define S5PC210_PA_ONENAND (0x0C000000) 31 - #define S5P_PA_ONENAND S5PC210_PA_ONENAND 38 + #define S5PC210_PA_ONENAND 0x0C000000 39 + #define S5PC210_PA_ONENAND_DMA 0x0C600000 32 40 33 - #define S5PC210_PA_ONENAND_DMA (0x0C600000) 34 - #define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA 41 + #define S5PV310_PA_CHIPID 0x10000000 35 42 36 - #define S5PV310_PA_CHIPID (0x10000000) 37 - #define S5P_PA_CHIPID S5PV310_PA_CHIPID 43 + #define S5PV310_PA_SYSCON 0x10010000 44 + #define S5PV310_PA_PMU 0x10020000 45 + #define S5PV310_PA_CMU 0x10030000 38 46 39 - #define S5PV310_PA_SYSCON (0x10010000) 40 - #define S5P_PA_SYSCON S5PV310_PA_SYSCON 47 + #define S5PV310_PA_WATCHDOG 0x10060000 48 + #define S5PV310_PA_RTC 0x10070000 41 49 42 - #define S5PV310_PA_PMU (0x10020000) 50 + #define S5PV310_PA_DMC0 0x10400000 43 51 44 - #define S5PV310_PA_CMU (0x10030000) 52 + #define S5PV310_PA_COMBINER 0x10448000 45 53 46 - #define S5PV310_PA_WATCHDOG (0x10060000) 47 - #define S5PV310_PA_RTC (0x10070000) 54 + #define S5PV310_PA_COREPERI 0x10500000 55 + #define S5PV310_PA_GIC_CPU 0x10500100 56 + #define S5PV310_PA_TWD 0x10500600 57 + #define S5PV310_PA_GIC_DIST 0x10501000 58 + #define S5PV310_PA_L2CC 0x10502000 48 59 49 - #define S5PV310_PA_DMC0 (0x10400000) 50 - 51 - #define S5PV310_PA_COMBINER (0x10448000) 52 - 53 - #define S5PV310_PA_COREPERI (0x10500000) 54 - #define S5PV310_PA_GIC_CPU (0x10500100) 55 - #define S5PV310_PA_TWD (0x10500600) 56 - #define S5PV310_PA_GIC_DIST (0x10501000) 57 - #define S5PV310_PA_L2CC (0x10502000) 58 - 59 - /* DMA */ 60 - #define S5PV310_PA_MDMA 0x10810000 61 - #define S5PV310_PA_PDMA0 0x12680000 62 - #define S5PV310_PA_PDMA1 0x12690000 63 - 64 - #define S5PV310_PA_GPIO1 (0x11400000) 65 - #define S5PV310_PA_GPIO2 (0x11000000) 66 - #define S5PV310_PA_GPIO3 (0x03860000) 67 - 68 - #define S5PV310_PA_MIPI_CSIS0 0x11880000 69 - #define S5PV310_PA_MIPI_CSIS1 0x11890000 70 - 71 - #define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 72 - 73 - #define S5PV310_PA_SROMC (0x12570000) 74 - #define S5P_PA_SROMC S5PV310_PA_SROMC 75 - 76 - /* S/PDIF */ 77 - #define S5PV310_PA_SPDIF 0xE1100000 78 - 79 - /* I2S */ 80 - #define S5PV310_PA_I2S0 0x03830000 81 - #define S5PV310_PA_I2S1 0xE3100000 82 - #define S5PV310_PA_I2S2 0xE2A00000 83 - 84 - /* PCM */ 85 - #define S5PV310_PA_PCM0 0x03840000 86 - #define S5PV310_PA_PCM1 0x13980000 87 - #define S5PV310_PA_PCM2 0x13990000 88 - 89 - /* AC97 */ 90 - #define S5PV310_PA_AC97 0x139A0000 91 - 92 - #define S5PV310_PA_UART (0x13800000) 93 - 94 - #define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET)) 95 - #define S5P_PA_UART0 S5P_PA_UART(0) 96 - #define S5P_PA_UART1 S5P_PA_UART(1) 97 - #define S5P_PA_UART2 S5P_PA_UART(2) 98 - #define S5P_PA_UART3 S5P_PA_UART(3) 99 - #define S5P_PA_UART4 S5P_PA_UART(4) 100 - 101 - #define S5P_SZ_UART SZ_256 102 - 103 - #define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 104 - 105 - #define S5PV310_PA_TIMER (0x139D0000) 106 - #define S5P_PA_TIMER S5PV310_PA_TIMER 107 - 108 - #define S5PV310_PA_SDRAM (0x40000000) 109 - #define S5P_PA_SDRAM S5PV310_PA_SDRAM 60 + #define S5PV310_PA_MDMA 0x10810000 61 + #define S5PV310_PA_PDMA0 0x12680000 62 + #define S5PV310_PA_PDMA1 0x12690000 110 63 111 64 #define S5PV310_PA_SYSMMU_MDMA 0x10A40000 112 65 #define S5PV310_PA_SYSMMU_SSS 0x10A50000 ··· 78 125 #define S5PV310_PA_SYSMMU_MFC_L 0x13620000 79 126 #define S5PV310_PA_SYSMMU_MFC_R 0x13630000 80 127 81 - /* compatibiltiy defines. */ 82 - #define S3C_PA_UART S5PV310_PA_UART 128 + #define S5PV310_PA_GPIO1 0x11400000 129 + #define S5PV310_PA_GPIO2 0x11000000 130 + #define S5PV310_PA_GPIO3 0x03860000 131 + 132 + #define S5PV310_PA_MIPI_CSIS0 0x11880000 133 + #define S5PV310_PA_MIPI_CSIS1 0x11890000 134 + 135 + #define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 136 + 137 + #define S5PV310_PA_SROMC 0x12570000 138 + 139 + #define S5PV310_PA_UART 0x13800000 140 + 141 + #define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 142 + 143 + #define S5PV310_PA_AC97 0x139A0000 144 + 145 + #define S5PV310_PA_TIMER 0x139D0000 146 + 147 + #define S5PV310_PA_SDRAM 0x40000000 148 + 149 + #define S5PV310_PA_SPDIF 0xE1100000 150 + 151 + /* Compatibiltiy Defines */ 152 + 83 153 #define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0) 84 154 #define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1) 85 155 #define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2) ··· 117 141 #define S3C_PA_IIC7 S5PV310_PA_IIC(7) 118 142 #define S3C_PA_RTC S5PV310_PA_RTC 119 143 #define S3C_PA_WDT S5PV310_PA_WATCHDOG 144 + 145 + #define S5P_PA_CHIPID S5PV310_PA_CHIPID 120 146 #define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0 121 147 #define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1 148 + #define S5P_PA_ONENAND S5PC210_PA_ONENAND 149 + #define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA 150 + #define S5P_PA_SDRAM S5PV310_PA_SDRAM 151 + #define S5P_PA_SROMC S5PV310_PA_SROMC 152 + #define S5P_PA_SYSCON S5PV310_PA_SYSCON 153 + #define S5P_PA_TIMER S5PV310_PA_TIMER 154 + 155 + /* UART */ 156 + 157 + #define S3C_PA_UART S5PV310_PA_UART 158 + 159 + #define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) 160 + #define S5P_PA_UART0 S5P_PA_UART(0) 161 + #define S5P_PA_UART1 S5P_PA_UART(1) 162 + #define S5P_PA_UART2 S5P_PA_UART(2) 163 + #define S5P_PA_UART3 S5P_PA_UART(3) 164 + #define S5P_PA_UART4 S5P_PA_UART(4) 165 + 166 + #define S5P_SZ_UART SZ_256 122 167 123 168 #endif /* __ASM_ARCH_MAP_H */

+6 -6

arch/arm/plat-s5p/dev-uart.c

··· 28 28 static struct resource s5p_uart0_resource[] = { 29 29 [0] = { 30 30 .start = S5P_PA_UART0, 31 - .end = S5P_PA_UART0 + S5P_SZ_UART, 31 + .end = S5P_PA_UART0 + S5P_SZ_UART - 1, 32 32 .flags = IORESOURCE_MEM, 33 33 }, 34 34 [1] = { ··· 51 51 static struct resource s5p_uart1_resource[] = { 52 52 [0] = { 53 53 .start = S5P_PA_UART1, 54 - .end = S5P_PA_UART1 + S5P_SZ_UART, 54 + .end = S5P_PA_UART1 + S5P_SZ_UART - 1, 55 55 .flags = IORESOURCE_MEM, 56 56 }, 57 57 [1] = { ··· 74 74 static struct resource s5p_uart2_resource[] = { 75 75 [0] = { 76 76 .start = S5P_PA_UART2, 77 - .end = S5P_PA_UART2 + S5P_SZ_UART, 77 + .end = S5P_PA_UART2 + S5P_SZ_UART - 1, 78 78 .flags = IORESOURCE_MEM, 79 79 }, 80 80 [1] = { ··· 98 98 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3 99 99 [0] = { 100 100 .start = S5P_PA_UART3, 101 - .end = S5P_PA_UART3 + S5P_SZ_UART, 101 + .end = S5P_PA_UART3 + S5P_SZ_UART - 1, 102 102 .flags = IORESOURCE_MEM, 103 103 }, 104 104 [1] = { ··· 123 123 #if CONFIG_SERIAL_SAMSUNG_UARTS > 4 124 124 [0] = { 125 125 .start = S5P_PA_UART4, 126 - .end = S5P_PA_UART4 + S5P_SZ_UART, 126 + .end = S5P_PA_UART4 + S5P_SZ_UART - 1, 127 127 .flags = IORESOURCE_MEM, 128 128 }, 129 129 [1] = { ··· 148 148 #if CONFIG_SERIAL_SAMSUNG_UARTS > 5 149 149 [0] = { 150 150 .start = S5P_PA_UART5, 151 - .end = S5P_PA_UART5 + S5P_SZ_UART, 151 + .end = S5P_PA_UART5 + S5P_SZ_UART - 1, 152 152 .flags = IORESOURCE_MEM, 153 153 }, 154 154 [1] = {

-1

arch/arm/plat-samsung/dev-ts.c

··· 58 58 59 59 s3c_device_ts.dev.platform_data = npd; 60 60 } 61 - EXPORT_SYMBOL(s3c24xx_ts_set_platdata);