Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S5PV210: Fix regulator names
ARM: S5PV210: Update max8998_platform_data
ARM: SAMSUNG: Drop exporting s3c24xx_ts_set_platdata
ARM: S5P: Fix end address in memory resource information for UART devices
ARM: S5P64X0: Cleanup map.h file
ARM: S5P6442: Cleanup map.h file
ARM: S5PC100: Clenaup map.h file
ARM: S5PV210: Cleanup map.h file
ARM: S5PV310: Cleanup map.h file
+38
-33
arch/arm/mach-s5p6442/include/mach/map.h
+38
-33
arch/arm/mach-s5p6442/include/mach/map.h
···
1
/* linux/arch/arm/mach-s5p6442/include/mach/map.h
2
*
3
-
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
4
* http://www.samsung.com/
5
*
6
* S5P6442 - Memory map definitions
···
16
#include <plat/map-base.h>
17
#include <plat/map-s5p.h>
18
19
-
#define S5P6442_PA_CHIPID (0xE0000000)
20
-
#define S5P_PA_CHIPID S5P6442_PA_CHIPID
21
22
-
#define S5P6442_PA_SYSCON (0xE0100000)
23
-
#define S5P_PA_SYSCON S5P6442_PA_SYSCON
24
25
-
#define S5P6442_PA_GPIO (0xE0200000)
26
27
-
#define S5P6442_PA_VIC0 (0xE4000000)
28
-
#define S5P6442_PA_VIC1 (0xE4100000)
29
-
#define S5P6442_PA_VIC2 (0xE4200000)
30
31
-
#define S5P6442_PA_SROMC (0xE7000000)
32
-
#define S5P_PA_SROMC S5P6442_PA_SROMC
33
34
#define S5P6442_PA_MDMA 0xE8000000
35
#define S5P6442_PA_PDMA 0xE9000000
36
37
-
#define S5P6442_PA_TIMER (0xEA000000)
38
-
#define S5P_PA_TIMER S5P6442_PA_TIMER
39
40
-
#define S5P6442_PA_SYSTIMER (0xEA100000)
41
42
-
#define S5P6442_PA_WATCHDOG (0xEA200000)
43
44
-
#define S5P6442_PA_UART (0xEC000000)
45
46
-
#define S5P_PA_UART0 (S5P6442_PA_UART + 0x0)
47
-
#define S5P_PA_UART1 (S5P6442_PA_UART + 0x400)
48
-
#define S5P_PA_UART2 (S5P6442_PA_UART + 0x800)
49
-
#define S5P_SZ_UART SZ_256
50
-
51
-
#define S5P6442_PA_IIC0 (0xEC100000)
52
-
53
-
#define S5P6442_PA_SDRAM (0x20000000)
54
-
#define S5P_PA_SDRAM S5P6442_PA_SDRAM
55
56
#define S5P6442_PA_SPI 0xEC300000
57
58
-
/* I2S */
59
-
#define S5P6442_PA_I2S0 0xC0B00000
60
-
#define S5P6442_PA_I2S1 0xF2200000
61
-
62
-
/* PCM */
63
#define S5P6442_PA_PCM0 0xF2400000
64
#define S5P6442_PA_PCM1 0xF2500000
65
66
-
/* compatibiltiy defines. */
67
-
#define S3C_PA_WDT S5P6442_PA_WATCHDOG
68
-
#define S3C_PA_UART S5P6442_PA_UART
69
#define S3C_PA_IIC S5P6442_PA_IIC0
70
71
#endif /* __ASM_ARCH_MAP_H */
···
1
/* linux/arch/arm/mach-s5p6442/include/mach/map.h
2
*
3
+
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4
* http://www.samsung.com/
5
*
6
* S5P6442 - Memory map definitions
···
16
#include <plat/map-base.h>
17
#include <plat/map-s5p.h>
18
19
+
#define S5P6442_PA_SDRAM 0x20000000
20
21
+
#define S5P6442_PA_I2S0 0xC0B00000
22
+
#define S5P6442_PA_I2S1 0xF2200000
23
24
+
#define S5P6442_PA_CHIPID 0xE0000000
25
26
+
#define S5P6442_PA_SYSCON 0xE0100000
27
28
+
#define S5P6442_PA_GPIO 0xE0200000
29
+
30
+
#define S5P6442_PA_VIC0 0xE4000000
31
+
#define S5P6442_PA_VIC1 0xE4100000
32
+
#define S5P6442_PA_VIC2 0xE4200000
33
+
34
+
#define S5P6442_PA_SROMC 0xE7000000
35
36
#define S5P6442_PA_MDMA 0xE8000000
37
#define S5P6442_PA_PDMA 0xE9000000
38
39
+
#define S5P6442_PA_TIMER 0xEA000000
40
41
+
#define S5P6442_PA_SYSTIMER 0xEA100000
42
43
+
#define S5P6442_PA_WATCHDOG 0xEA200000
44
45
+
#define S5P6442_PA_UART 0xEC000000
46
47
+
#define S5P6442_PA_IIC0 0xEC100000
48
49
#define S5P6442_PA_SPI 0xEC300000
50
51
#define S5P6442_PA_PCM0 0xF2400000
52
#define S5P6442_PA_PCM1 0xF2500000
53
54
+
/* Compatibiltiy Defines */
55
+
56
#define S3C_PA_IIC S5P6442_PA_IIC0
57
+
#define S3C_PA_WDT S5P6442_PA_WATCHDOG
58
+
59
+
#define S5P_PA_CHIPID S5P6442_PA_CHIPID
60
+
#define S5P_PA_SDRAM S5P6442_PA_SDRAM
61
+
#define S5P_PA_SROMC S5P6442_PA_SROMC
62
+
#define S5P_PA_SYSCON S5P6442_PA_SYSCON
63
+
#define S5P_PA_TIMER S5P6442_PA_TIMER
64
+
65
+
/* UART */
66
+
67
+
#define S3C_PA_UART S5P6442_PA_UART
68
+
69
+
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
70
+
#define S5P_PA_UART0 S5P_PA_UART(0)
71
+
#define S5P_PA_UART1 S5P_PA_UART(1)
72
+
#define S5P_PA_UART2 S5P_PA_UART(2)
73
+
74
+
#define S5P_SZ_UART SZ_256
75
76
#endif /* __ASM_ARCH_MAP_H */
+52
-51
arch/arm/mach-s5p64x0/include/mach/map.h
+52
-51
arch/arm/mach-s5p64x0/include/mach/map.h
···
1
/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
2
*
3
-
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4
* http://www.samsung.com
5
*
6
* S5P64X0 - Memory map definitions
···
16
#include <plat/map-base.h>
17
#include <plat/map-s5p.h>
18
19
-
#define S5P64X0_PA_SDRAM (0x20000000)
20
21
-
#define S5P64X0_PA_CHIPID (0xE0000000)
22
#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
23
-
24
-
#define S5P64X0_PA_SYSCON (0xE0100000)
25
-
#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
26
-
27
-
#define S5P64X0_PA_GPIO (0xE0308000)
28
-
29
-
#define S5P64X0_PA_VIC0 (0xE4000000)
30
-
#define S5P64X0_PA_VIC1 (0xE4100000)
31
-
32
-
#define S5P64X0_PA_SROMC (0xE7000000)
33
#define S5P_PA_SROMC S5P64X0_PA_SROMC
34
-
35
-
#define S5P64X0_PA_PDMA (0xE9000000)
36
-
37
-
#define S5P64X0_PA_TIMER (0xEA000000)
38
#define S5P_PA_TIMER S5P64X0_PA_TIMER
39
40
-
#define S5P64X0_PA_RTC (0xEA100000)
41
42
-
#define S5P64X0_PA_WDT (0xEA200000)
43
44
#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
45
#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
···
85
#define S5P_PA_UART5 S5P6450_PA_UART(5)
86
87
#define S5P_SZ_UART SZ_256
88
-
89
-
#define S5P6440_PA_IIC0 (0xEC104000)
90
-
#define S5P6440_PA_IIC1 (0xEC20F000)
91
-
#define S5P6450_PA_IIC0 (0xEC100000)
92
-
#define S5P6450_PA_IIC1 (0xEC200000)
93
-
94
-
#define S5P64X0_PA_SPI0 (0xEC400000)
95
-
#define S5P64X0_PA_SPI1 (0xEC500000)
96
-
97
-
#define S5P64X0_PA_HSOTG (0xED100000)
98
-
99
-
#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
100
-
101
-
#define S5P64X0_PA_I2S (0xF2000000)
102
-
#define S5P6450_PA_I2S1 0xF2800000
103
-
#define S5P6450_PA_I2S2 0xF2900000
104
-
105
-
#define S5P64X0_PA_PCM (0xF2100000)
106
-
107
-
#define S5P64X0_PA_ADC (0xF3000000)
108
-
109
-
/* compatibiltiy defines. */
110
-
111
-
#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
112
-
#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
113
-
#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
114
-
#define S3C_PA_IIC S5P6440_PA_IIC0
115
-
#define S3C_PA_IIC1 S5P6440_PA_IIC1
116
-
#define S3C_PA_RTC S5P64X0_PA_RTC
117
-
#define S3C_PA_WDT S5P64X0_PA_WDT
118
-
119
-
#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
120
121
#endif /* __ASM_ARCH_MAP_H */
···
1
/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
2
*
3
+
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4
* http://www.samsung.com
5
*
6
* S5P64X0 - Memory map definitions
···
16
#include <plat/map-base.h>
17
#include <plat/map-s5p.h>
18
19
+
#define S5P64X0_PA_SDRAM 0x20000000
20
21
+
#define S5P64X0_PA_CHIPID 0xE0000000
22
+
23
+
#define S5P64X0_PA_SYSCON 0xE0100000
24
+
25
+
#define S5P64X0_PA_GPIO 0xE0308000
26
+
27
+
#define S5P64X0_PA_VIC0 0xE4000000
28
+
#define S5P64X0_PA_VIC1 0xE4100000
29
+
30
+
#define S5P64X0_PA_SROMC 0xE7000000
31
+
32
+
#define S5P64X0_PA_PDMA 0xE9000000
33
+
34
+
#define S5P64X0_PA_TIMER 0xEA000000
35
+
#define S5P64X0_PA_RTC 0xEA100000
36
+
#define S5P64X0_PA_WDT 0xEA200000
37
+
38
+
#define S5P6440_PA_IIC0 0xEC104000
39
+
#define S5P6440_PA_IIC1 0xEC20F000
40
+
#define S5P6450_PA_IIC0 0xEC100000
41
+
#define S5P6450_PA_IIC1 0xEC200000
42
+
43
+
#define S5P64X0_PA_SPI0 0xEC400000
44
+
#define S5P64X0_PA_SPI1 0xEC500000
45
+
46
+
#define S5P64X0_PA_HSOTG 0xED100000
47
+
48
+
#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
49
+
50
+
#define S5P64X0_PA_I2S 0xF2000000
51
+
#define S5P6450_PA_I2S1 0xF2800000
52
+
#define S5P6450_PA_I2S2 0xF2900000
53
+
54
+
#define S5P64X0_PA_PCM 0xF2100000
55
+
56
+
#define S5P64X0_PA_ADC 0xF3000000
57
+
58
+
/* Compatibiltiy Defines */
59
+
60
+
#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
61
+
#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
62
+
#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
63
+
#define S3C_PA_IIC S5P6440_PA_IIC0
64
+
#define S3C_PA_IIC1 S5P6440_PA_IIC1
65
+
#define S3C_PA_RTC S5P64X0_PA_RTC
66
+
#define S3C_PA_WDT S5P64X0_PA_WDT
67
+
68
#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
69
#define S5P_PA_SROMC S5P64X0_PA_SROMC
70
+
#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
71
#define S5P_PA_TIMER S5P64X0_PA_TIMER
72
73
+
#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
74
75
+
/* UART */
76
77
#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
78
#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
···
52
#define S5P_PA_UART5 S5P6450_PA_UART(5)
53
54
#define S5P_SZ_UART SZ_256
55
56
#endif /* __ASM_ARCH_MAP_H */
+82
-109
arch/arm/mach-s5pc100/include/mach/map.h
+82
-109
arch/arm/mach-s5pc100/include/mach/map.h
···
1
/* linux/arch/arm/mach-s5pc100/include/mach/map.h
2
*
3
* Copyright 2009 Samsung Electronics Co.
4
* Byungho Min <bhmin@samsung.com>
5
*
···
19
#include <plat/map-base.h>
20
#include <plat/map-s5p.h>
21
22
-
/*
23
-
* map-base.h has already defined virtual memory address
24
-
* S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s)
25
-
* S3C_VA_SYS S3C_ADDR(0x00100000) system control
26
-
* S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used)
27
-
* S3C_VA_TIMER S3C_ADDR(0x00300000) timer block
28
-
* S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
29
-
* S3C_VA_UART S3C_ADDR(0x01000000) UART
30
-
*
31
-
* S5PC100 specific virtual memory address can be defined here
32
-
* S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
33
-
*
34
-
*/
35
36
-
#define S5PC100_PA_ONENAND_BUF (0xB0000000)
37
-
#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
38
39
-
/* Chip ID */
40
41
-
#define S5PC100_PA_CHIPID (0xE0000000)
42
-
#define S5P_PA_CHIPID S5PC100_PA_CHIPID
43
44
-
#define S5PC100_PA_SYSCON (0xE0100000)
45
-
#define S5P_PA_SYSCON S5PC100_PA_SYSCON
46
47
-
#define S5PC100_PA_OTHERS (0xE0200000)
48
-
#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
49
50
-
#define S5PC100_PA_GPIO (0xE0300000)
51
-
#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
52
53
-
/* Interrupt */
54
-
#define S5PC100_PA_VIC0 (0xE4000000)
55
-
#define S5PC100_PA_VIC1 (0xE4100000)
56
-
#define S5PC100_PA_VIC2 (0xE4200000)
57
-
#define S5PC100_VA_VIC S3C_VA_IRQ
58
-
#define S5PC100_VA_VIC_OFFSET 0x10000
59
-
#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
60
61
-
#define S5PC100_PA_SROMC (0xE7000000)
62
-
#define S5P_PA_SROMC S5PC100_PA_SROMC
63
64
-
#define S5PC100_PA_ONENAND (0xE7100000)
65
66
-
#define S5PC100_PA_CFCON (0xE7800000)
67
68
-
/* DMA */
69
-
#define S5PC100_PA_MDMA (0xE8100000)
70
-
#define S5PC100_PA_PDMA0 (0xE9000000)
71
-
#define S5PC100_PA_PDMA1 (0xE9200000)
72
73
-
/* Timer */
74
-
#define S5PC100_PA_TIMER (0xEA000000)
75
-
#define S5P_PA_TIMER S5PC100_PA_TIMER
76
77
-
#define S5PC100_PA_SYSTIMER (0xEA100000)
78
79
-
#define S5PC100_PA_WATCHDOG (0xEA200000)
80
-
#define S5PC100_PA_RTC (0xEA300000)
81
82
-
#define S5PC100_PA_UART (0xEC000000)
83
84
-
#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0)
85
-
#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400)
86
-
#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800)
87
-
#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00)
88
-
#define S5P_SZ_UART SZ_256
89
90
-
#define S5PC100_PA_IIC0 (0xEC100000)
91
-
#define S5PC100_PA_IIC1 (0xEC200000)
92
93
-
/* SPI */
94
-
#define S5PC100_PA_SPI0 0xEC300000
95
-
#define S5PC100_PA_SPI1 0xEC400000
96
-
#define S5PC100_PA_SPI2 0xEC500000
97
98
-
/* USB HS OTG */
99
-
#define S5PC100_PA_USB_HSOTG (0xED200000)
100
-
#define S5PC100_PA_USB_HSPHY (0xED300000)
101
102
-
#define S5PC100_PA_FB (0xEE000000)
103
104
-
#define S5PC100_PA_FIMC0 (0xEE200000)
105
-
#define S5PC100_PA_FIMC1 (0xEE300000)
106
-
#define S5PC100_PA_FIMC2 (0xEE400000)
107
108
-
#define S5PC100_PA_I2S0 (0xF2000000)
109
-
#define S5PC100_PA_I2S1 (0xF2100000)
110
-
#define S5PC100_PA_I2S2 (0xF2200000)
111
112
-
#define S5PC100_PA_AC97 0xF2300000
113
114
-
/* PCM */
115
-
#define S5PC100_PA_PCM0 0xF2400000
116
-
#define S5PC100_PA_PCM1 0xF2500000
117
118
-
#define S5PC100_PA_SPDIF 0xF2600000
119
120
-
#define S5PC100_PA_TSADC (0xF3000000)
121
122
-
/* KEYPAD */
123
-
#define S5PC100_PA_KEYPAD (0xF3100000)
124
125
-
#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
126
127
-
#define S5PC100_PA_SDRAM (0x20000000)
128
-
#define S5P_PA_SDRAM S5PC100_PA_SDRAM
129
130
-
/* compatibiltiy defines. */
131
-
#define S3C_PA_UART S5PC100_PA_UART
132
-
#define S3C_PA_IIC S5PC100_PA_IIC0
133
-
#define S3C_PA_IIC1 S5PC100_PA_IIC1
134
-
#define S3C_PA_FB S5PC100_PA_FB
135
-
#define S3C_PA_G2D S5PC100_PA_G2D
136
-
#define S3C_PA_G3D S5PC100_PA_G3D
137
-
#define S3C_PA_JPEG S5PC100_PA_JPEG
138
-
#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
139
-
#define S5P_VA_VIC0 S5PC1XX_VA_VIC(0)
140
-
#define S5P_VA_VIC1 S5PC1XX_VA_VIC(1)
141
-
#define S5P_VA_VIC2 S5PC1XX_VA_VIC(2)
142
-
#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
143
-
#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
144
-
#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
145
-
#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
146
-
#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
147
-
#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
148
-
#define S3C_PA_WDT S5PC100_PA_WATCHDOG
149
-
#define S3C_PA_TSADC S5PC100_PA_TSADC
150
-
#define S3C_PA_ONENAND S5PC100_PA_ONENAND
151
-
#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
152
-
#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
153
-
#define S3C_PA_RTC S5PC100_PA_RTC
154
155
-
#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
156
-
#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
157
-
#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
158
159
-
#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
160
-
#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
161
-
#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
162
163
-
#endif /* __ASM_ARCH_C100_MAP_H */
···
1
/* linux/arch/arm/mach-s5pc100/include/mach/map.h
2
*
3
+
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
4
+
* http://www.samsung.com/
5
+
*
6
* Copyright 2009 Samsung Electronics Co.
7
* Byungho Min <bhmin@samsung.com>
8
*
···
16
#include <plat/map-base.h>
17
#include <plat/map-s5p.h>
18
19
+
#define S5PC100_PA_SDRAM 0x20000000
20
21
+
#define S5PC100_PA_ONENAND 0xE7100000
22
+
#define S5PC100_PA_ONENAND_BUF 0xB0000000
23
24
+
#define S5PC100_PA_CHIPID 0xE0000000
25
26
+
#define S5PC100_PA_SYSCON 0xE0100000
27
28
+
#define S5PC100_PA_OTHERS 0xE0200000
29
30
+
#define S5PC100_PA_GPIO 0xE0300000
31
32
+
#define S5PC100_PA_VIC0 0xE4000000
33
+
#define S5PC100_PA_VIC1 0xE4100000
34
+
#define S5PC100_PA_VIC2 0xE4200000
35
36
+
#define S5PC100_PA_SROMC 0xE7000000
37
38
+
#define S5PC100_PA_CFCON 0xE7800000
39
40
+
#define S5PC100_PA_MDMA 0xE8100000
41
+
#define S5PC100_PA_PDMA0 0xE9000000
42
+
#define S5PC100_PA_PDMA1 0xE9200000
43
44
+
#define S5PC100_PA_TIMER 0xEA000000
45
+
#define S5PC100_PA_SYSTIMER 0xEA100000
46
+
#define S5PC100_PA_WATCHDOG 0xEA200000
47
+
#define S5PC100_PA_RTC 0xEA300000
48
49
+
#define S5PC100_PA_UART 0xEC000000
50
51
+
#define S5PC100_PA_IIC0 0xEC100000
52
+
#define S5PC100_PA_IIC1 0xEC200000
53
54
+
#define S5PC100_PA_SPI0 0xEC300000
55
+
#define S5PC100_PA_SPI1 0xEC400000
56
+
#define S5PC100_PA_SPI2 0xEC500000
57
58
+
#define S5PC100_PA_USB_HSOTG 0xED200000
59
+
#define S5PC100_PA_USB_HSPHY 0xED300000
60
61
+
#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
62
63
+
#define S5PC100_PA_FB 0xEE000000
64
65
+
#define S5PC100_PA_FIMC0 0xEE200000
66
+
#define S5PC100_PA_FIMC1 0xEE300000
67
+
#define S5PC100_PA_FIMC2 0xEE400000
68
69
+
#define S5PC100_PA_I2S0 0xF2000000
70
+
#define S5PC100_PA_I2S1 0xF2100000
71
+
#define S5PC100_PA_I2S2 0xF2200000
72
73
+
#define S5PC100_PA_AC97 0xF2300000
74
75
+
#define S5PC100_PA_PCM0 0xF2400000
76
+
#define S5PC100_PA_PCM1 0xF2500000
77
78
+
#define S5PC100_PA_SPDIF 0xF2600000
79
80
+
#define S5PC100_PA_TSADC 0xF3000000
81
82
+
#define S5PC100_PA_KEYPAD 0xF3100000
83
84
+
/* Compatibiltiy Defines */
85
86
+
#define S3C_PA_FB S5PC100_PA_FB
87
+
#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
88
+
#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
89
+
#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
90
+
#define S3C_PA_IIC S5PC100_PA_IIC0
91
+
#define S3C_PA_IIC1 S5PC100_PA_IIC1
92
+
#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
93
+
#define S3C_PA_ONENAND S5PC100_PA_ONENAND
94
+
#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
95
+
#define S3C_PA_RTC S5PC100_PA_RTC
96
+
#define S3C_PA_TSADC S5PC100_PA_TSADC
97
+
#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
98
+
#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
99
+
#define S3C_PA_WDT S5PC100_PA_WATCHDOG
100
101
+
#define S5P_PA_CHIPID S5PC100_PA_CHIPID
102
+
#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
103
+
#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
104
+
#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
105
+
#define S5P_PA_SDRAM S5PC100_PA_SDRAM
106
+
#define S5P_PA_SROMC S5PC100_PA_SROMC
107
+
#define S5P_PA_SYSCON S5PC100_PA_SYSCON
108
+
#define S5P_PA_TIMER S5PC100_PA_TIMER
109
110
+
#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
111
+
#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
112
+
#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
113
114
+
#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
115
116
+
#define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
117
118
+
/* UART */
119
120
+
#define S3C_PA_UART S5PC100_PA_UART
121
122
+
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
123
+
#define S5P_PA_UART0 S5P_PA_UART(0)
124
+
#define S5P_PA_UART1 S5P_PA_UART(1)
125
+
#define S5P_PA_UART2 S5P_PA_UART(2)
126
+
#define S5P_PA_UART3 S5P_PA_UART(3)
127
128
+
#define S5P_SZ_UART SZ_256
129
+
130
+
#endif /* __ASM_ARCH_MAP_H */
+83
-85
arch/arm/mach-s5pv210/include/mach/map.h
+83
-85
arch/arm/mach-s5pv210/include/mach/map.h
···
1
/* linux/arch/arm/mach-s5pv210/include/mach/map.h
2
*
3
-
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
4
* http://www.samsung.com/
5
*
6
* S5PV210 - Memory map definitions
···
16
#include <plat/map-base.h>
17
#include <plat/map-s5p.h>
18
19
-
#define S5PV210_PA_SROM_BANK5 (0xA8000000)
20
21
-
#define S5PC110_PA_ONENAND (0xB0000000)
22
-
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
23
24
-
#define S5PC110_PA_ONENAND_DMA (0xB0600000)
25
-
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
26
27
-
#define S5PV210_PA_CHIPID (0xE0000000)
28
-
#define S5P_PA_CHIPID S5PV210_PA_CHIPID
29
30
-
#define S5PV210_PA_SYSCON (0xE0100000)
31
-
#define S5P_PA_SYSCON S5PV210_PA_SYSCON
32
33
-
#define S5PV210_PA_GPIO (0xE0200000)
34
35
-
/* SPI */
36
-
#define S5PV210_PA_SPI0 0xE1300000
37
-
#define S5PV210_PA_SPI1 0xE1400000
38
39
-
#define S5PV210_PA_KEYPAD (0xE1600000)
40
41
-
#define S5PV210_PA_IIC0 (0xE1800000)
42
-
#define S5PV210_PA_IIC1 (0xFAB00000)
43
-
#define S5PV210_PA_IIC2 (0xE1A00000)
44
45
-
#define S5PV210_PA_TIMER (0xE2500000)
46
-
#define S5P_PA_TIMER S5PV210_PA_TIMER
47
48
-
#define S5PV210_PA_SYSTIMER (0xE2600000)
49
50
-
#define S5PV210_PA_WATCHDOG (0xE2700000)
51
52
-
#define S5PV210_PA_RTC (0xE2800000)
53
-
#define S5PV210_PA_UART (0xE2900000)
54
55
-
#define S5P_PA_UART0 (S5PV210_PA_UART + 0x0)
56
-
#define S5P_PA_UART1 (S5PV210_PA_UART + 0x400)
57
-
#define S5P_PA_UART2 (S5PV210_PA_UART + 0x800)
58
-
#define S5P_PA_UART3 (S5PV210_PA_UART + 0xC00)
59
60
-
#define S5P_SZ_UART SZ_256
61
62
-
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
63
64
-
#define S5PV210_PA_SROMC (0xE8000000)
65
-
#define S5P_PA_SROMC S5PV210_PA_SROMC
66
67
-
#define S5PV210_PA_CFCON (0xE8200000)
68
69
-
#define S5PV210_PA_MDMA 0xFA200000
70
-
#define S5PV210_PA_PDMA0 0xE0900000
71
-
#define S5PV210_PA_PDMA1 0xE0A00000
72
73
-
#define S5PV210_PA_FB (0xF8000000)
74
75
-
#define S5PV210_PA_FIMC0 (0xFB200000)
76
-
#define S5PV210_PA_FIMC1 (0xFB300000)
77
-
#define S5PV210_PA_FIMC2 (0xFB400000)
78
79
-
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
80
81
-
#define S5PV210_PA_HSOTG (0xEC000000)
82
-
#define S5PV210_PA_HSPHY (0xEC100000)
83
84
-
#define S5PV210_PA_VIC0 (0xF2000000)
85
-
#define S5PV210_PA_VIC1 (0xF2100000)
86
-
#define S5PV210_PA_VIC2 (0xF2200000)
87
-
#define S5PV210_PA_VIC3 (0xF2300000)
88
89
-
#define S5PV210_PA_SDRAM (0x20000000)
90
-
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
91
92
-
/* S/PDIF */
93
-
#define S5PV210_PA_SPDIF 0xE1100000
94
95
-
/* I2S */
96
-
#define S5PV210_PA_IIS0 0xEEE30000
97
-
#define S5PV210_PA_IIS1 0xE2100000
98
-
#define S5PV210_PA_IIS2 0xE2A00000
99
100
-
/* PCM */
101
-
#define S5PV210_PA_PCM0 0xE2300000
102
-
#define S5PV210_PA_PCM1 0xE1200000
103
-
#define S5PV210_PA_PCM2 0xE2B00000
104
105
-
/* AC97 */
106
-
#define S5PV210_PA_AC97 0xE2200000
107
108
-
#define S5PV210_PA_ADC (0xE1700000)
109
110
-
#define S5PV210_PA_DMC0 (0xF0000000)
111
-
#define S5PV210_PA_DMC1 (0xF1400000)
112
113
-
#define S5PV210_PA_MIPI_CSIS 0xFA600000
114
115
-
/* compatibiltiy defines. */
116
-
#define S3C_PA_UART S5PV210_PA_UART
117
-
#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
118
-
#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
119
-
#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
120
-
#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
121
-
#define S3C_PA_IIC S5PV210_PA_IIC0
122
-
#define S3C_PA_IIC1 S5PV210_PA_IIC1
123
-
#define S3C_PA_IIC2 S5PV210_PA_IIC2
124
-
#define S3C_PA_FB S5PV210_PA_FB
125
-
#define S3C_PA_RTC S5PV210_PA_RTC
126
-
#define S3C_PA_WDT S5PV210_PA_WATCHDOG
127
-
#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
128
-
#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
129
-
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
130
-
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
131
-
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
132
133
-
#define SAMSUNG_PA_ADC S5PV210_PA_ADC
134
-
#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
135
-
#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
136
137
#endif /* __ASM_ARCH_MAP_H */
···
1
/* linux/arch/arm/mach-s5pv210/include/mach/map.h
2
*
3
+
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4
* http://www.samsung.com/
5
*
6
* S5PV210 - Memory map definitions
···
16
#include <plat/map-base.h>
17
#include <plat/map-s5p.h>
18
19
+
#define S5PV210_PA_SDRAM 0x20000000
20
21
+
#define S5PV210_PA_SROM_BANK5 0xA8000000
22
23
+
#define S5PC110_PA_ONENAND 0xB0000000
24
+
#define S5PC110_PA_ONENAND_DMA 0xB0600000
25
26
+
#define S5PV210_PA_CHIPID 0xE0000000
27
28
+
#define S5PV210_PA_SYSCON 0xE0100000
29
30
+
#define S5PV210_PA_GPIO 0xE0200000
31
32
+
#define S5PV210_PA_SPDIF 0xE1100000
33
34
+
#define S5PV210_PA_SPI0 0xE1300000
35
+
#define S5PV210_PA_SPI1 0xE1400000
36
37
+
#define S5PV210_PA_KEYPAD 0xE1600000
38
39
+
#define S5PV210_PA_ADC 0xE1700000
40
41
+
#define S5PV210_PA_IIC0 0xE1800000
42
+
#define S5PV210_PA_IIC1 0xFAB00000
43
+
#define S5PV210_PA_IIC2 0xE1A00000
44
45
+
#define S5PV210_PA_AC97 0xE2200000
46
47
+
#define S5PV210_PA_PCM0 0xE2300000
48
+
#define S5PV210_PA_PCM1 0xE1200000
49
+
#define S5PV210_PA_PCM2 0xE2B00000
50
51
+
#define S5PV210_PA_TIMER 0xE2500000
52
+
#define S5PV210_PA_SYSTIMER 0xE2600000
53
+
#define S5PV210_PA_WATCHDOG 0xE2700000
54
+
#define S5PV210_PA_RTC 0xE2800000
55
56
+
#define S5PV210_PA_UART 0xE2900000
57
58
+
#define S5PV210_PA_SROMC 0xE8000000
59
60
+
#define S5PV210_PA_CFCON 0xE8200000
61
62
+
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
63
64
+
#define S5PV210_PA_HSOTG 0xEC000000
65
+
#define S5PV210_PA_HSPHY 0xEC100000
66
67
+
#define S5PV210_PA_IIS0 0xEEE30000
68
+
#define S5PV210_PA_IIS1 0xE2100000
69
+
#define S5PV210_PA_IIS2 0xE2A00000
70
71
+
#define S5PV210_PA_DMC0 0xF0000000
72
+
#define S5PV210_PA_DMC1 0xF1400000
73
74
+
#define S5PV210_PA_VIC0 0xF2000000
75
+
#define S5PV210_PA_VIC1 0xF2100000
76
+
#define S5PV210_PA_VIC2 0xF2200000
77
+
#define S5PV210_PA_VIC3 0xF2300000
78
79
+
#define S5PV210_PA_FB 0xF8000000
80
81
+
#define S5PV210_PA_MDMA 0xFA200000
82
+
#define S5PV210_PA_PDMA0 0xE0900000
83
+
#define S5PV210_PA_PDMA1 0xE0A00000
84
85
+
#define S5PV210_PA_MIPI_CSIS 0xFA600000
86
87
+
#define S5PV210_PA_FIMC0 0xFB200000
88
+
#define S5PV210_PA_FIMC1 0xFB300000
89
+
#define S5PV210_PA_FIMC2 0xFB400000
90
91
+
/* Compatibiltiy Defines */
92
93
+
#define S3C_PA_FB S5PV210_PA_FB
94
+
#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
95
+
#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
96
+
#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
97
+
#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
98
+
#define S3C_PA_IIC S5PV210_PA_IIC0
99
+
#define S3C_PA_IIC1 S5PV210_PA_IIC1
100
+
#define S3C_PA_IIC2 S5PV210_PA_IIC2
101
+
#define S3C_PA_RTC S5PV210_PA_RTC
102
+
#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
103
+
#define S3C_PA_WDT S5PV210_PA_WATCHDOG
104
105
+
#define S5P_PA_CHIPID S5PV210_PA_CHIPID
106
+
#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
107
+
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
108
+
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
109
+
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
110
+
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
111
+
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
112
+
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
113
+
#define S5P_PA_SROMC S5PV210_PA_SROMC
114
+
#define S5P_PA_SYSCON S5PV210_PA_SYSCON
115
+
#define S5P_PA_TIMER S5PV210_PA_TIMER
116
117
+
#define SAMSUNG_PA_ADC S5PV210_PA_ADC
118
+
#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
119
+
#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
120
121
+
/* UART */
122
123
+
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
124
125
+
#define S3C_PA_UART S5PV210_PA_UART
126
127
+
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
128
+
#define S5P_PA_UART0 S5P_PA_UART(0)
129
+
#define S5P_PA_UART1 S5P_PA_UART(1)
130
+
#define S5P_PA_UART2 S5P_PA_UART(2)
131
+
#define S5P_PA_UART3 S5P_PA_UART(3)
132
+
133
+
#define S5P_SZ_UART SZ_256
134
135
#endif /* __ASM_ARCH_MAP_H */
+9
-6
arch/arm/mach-s5pv210/mach-aquila.c
+9
-6
arch/arm/mach-s5pv210/mach-aquila.c
···
149
150
static struct regulator_init_data aquila_ldo3_data = {
151
.constraints = {
152
-
.name = "VUSB/MIPI_1.1V",
153
.min_uV = 1100000,
154
.max_uV = 1100000,
155
.apply_uV = 1,
···
197
198
static struct regulator_init_data aquila_ldo8_data = {
199
.constraints = {
200
-
.name = "VUSB/VADC_3.3V",
201
.min_uV = 3300000,
202
.max_uV = 3300000,
203
.apply_uV = 1,
···
207
208
static struct regulator_init_data aquila_ldo9_data = {
209
.constraints = {
210
-
.name = "VCC/VCAM_2.8V",
211
.min_uV = 2800000,
212
.max_uV = 2800000,
213
.apply_uV = 1,
···
381
.buck1_set1 = S5PV210_GPH0(3),
382
.buck1_set2 = S5PV210_GPH0(4),
383
.buck2_set3 = S5PV210_GPH0(5),
384
-
.buck1_max_voltage1 = 1200000,
385
-
.buck1_max_voltage2 = 1200000,
386
-
.buck2_max_voltage = 1200000,
387
};
388
#endif
389
···
149
150
static struct regulator_init_data aquila_ldo3_data = {
151
.constraints = {
152
+
.name = "VUSB+MIPI_1.1V",
153
.min_uV = 1100000,
154
.max_uV = 1100000,
155
.apply_uV = 1,
···
197
198
static struct regulator_init_data aquila_ldo8_data = {
199
.constraints = {
200
+
.name = "VUSB+VADC_3.3V",
201
.min_uV = 3300000,
202
.max_uV = 3300000,
203
.apply_uV = 1,
···
207
208
static struct regulator_init_data aquila_ldo9_data = {
209
.constraints = {
210
+
.name = "VCC+VCAM_2.8V",
211
.min_uV = 2800000,
212
.max_uV = 2800000,
213
.apply_uV = 1,
···
381
.buck1_set1 = S5PV210_GPH0(3),
382
.buck1_set2 = S5PV210_GPH0(4),
383
.buck2_set3 = S5PV210_GPH0(5),
384
+
.buck1_voltage1 = 1200000,
385
+
.buck1_voltage2 = 1200000,
386
+
.buck1_voltage3 = 1200000,
387
+
.buck1_voltage4 = 1200000,
388
+
.buck2_voltage1 = 1200000,
389
+
.buck2_voltage2 = 1200000,
390
};
391
#endif
392
+9
-6
arch/arm/mach-s5pv210/mach-goni.c
+9
-6
arch/arm/mach-s5pv210/mach-goni.c
···
288
289
static struct regulator_init_data goni_ldo3_data = {
290
.constraints = {
291
-
.name = "VUSB/MIPI_1.1V",
292
.min_uV = 1100000,
293
.max_uV = 1100000,
294
.apply_uV = 1,
···
337
338
static struct regulator_init_data goni_ldo8_data = {
339
.constraints = {
340
-
.name = "VUSB/VADC_3.3V",
341
.min_uV = 3300000,
342
.max_uV = 3300000,
343
.apply_uV = 1,
···
347
348
static struct regulator_init_data goni_ldo9_data = {
349
.constraints = {
350
-
.name = "VCC/VCAM_2.8V",
351
.min_uV = 2800000,
352
.max_uV = 2800000,
353
.apply_uV = 1,
···
521
.buck1_set1 = S5PV210_GPH0(3),
522
.buck1_set2 = S5PV210_GPH0(4),
523
.buck2_set3 = S5PV210_GPH0(5),
524
-
.buck1_max_voltage1 = 1200000,
525
-
.buck1_max_voltage2 = 1200000,
526
-
.buck2_max_voltage = 1200000,
527
};
528
#endif
529
···
288
289
static struct regulator_init_data goni_ldo3_data = {
290
.constraints = {
291
+
.name = "VUSB+MIPI_1.1V",
292
.min_uV = 1100000,
293
.max_uV = 1100000,
294
.apply_uV = 1,
···
337
338
static struct regulator_init_data goni_ldo8_data = {
339
.constraints = {
340
+
.name = "VUSB+VADC_3.3V",
341
.min_uV = 3300000,
342
.max_uV = 3300000,
343
.apply_uV = 1,
···
347
348
static struct regulator_init_data goni_ldo9_data = {
349
.constraints = {
350
+
.name = "VCC+VCAM_2.8V",
351
.min_uV = 2800000,
352
.max_uV = 2800000,
353
.apply_uV = 1,
···
521
.buck1_set1 = S5PV210_GPH0(3),
522
.buck1_set2 = S5PV210_GPH0(4),
523
.buck2_set3 = S5PV210_GPH0(5),
524
+
.buck1_voltage1 = 1200000,
525
+
.buck1_voltage2 = 1200000,
526
+
.buck1_voltage3 = 1200000,
527
+
.buck1_voltage4 = 1200000,
528
+
.buck2_voltage1 = 1200000,
529
+
.buck2_voltage2 = 1200000,
530
};
531
#endif
532
+74
-77
arch/arm/mach-s5pv310/include/mach/map.h
+74
-77
arch/arm/mach-s5pv310/include/mach/map.h
···
1
/* linux/arch/arm/mach-s5pv310/include/mach/map.h
2
*
3
-
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
4
* http://www.samsung.com/
5
*
6
* S5PV310 - Memory map definitions
···
23
24
#include <plat/map-s5p.h>
25
26
-
#define S5PV310_PA_SYSRAM (0x02025000)
27
28
#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
29
30
-
#define S5PC210_PA_ONENAND (0x0C000000)
31
-
#define S5P_PA_ONENAND S5PC210_PA_ONENAND
32
33
-
#define S5PC210_PA_ONENAND_DMA (0x0C600000)
34
-
#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
35
36
-
#define S5PV310_PA_CHIPID (0x10000000)
37
-
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
38
39
-
#define S5PV310_PA_SYSCON (0x10010000)
40
-
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
41
42
-
#define S5PV310_PA_PMU (0x10020000)
43
44
-
#define S5PV310_PA_CMU (0x10030000)
45
46
-
#define S5PV310_PA_WATCHDOG (0x10060000)
47
-
#define S5PV310_PA_RTC (0x10070000)
48
49
-
#define S5PV310_PA_DMC0 (0x10400000)
50
-
51
-
#define S5PV310_PA_COMBINER (0x10448000)
52
-
53
-
#define S5PV310_PA_COREPERI (0x10500000)
54
-
#define S5PV310_PA_GIC_CPU (0x10500100)
55
-
#define S5PV310_PA_TWD (0x10500600)
56
-
#define S5PV310_PA_GIC_DIST (0x10501000)
57
-
#define S5PV310_PA_L2CC (0x10502000)
58
-
59
-
/* DMA */
60
-
#define S5PV310_PA_MDMA 0x10810000
61
-
#define S5PV310_PA_PDMA0 0x12680000
62
-
#define S5PV310_PA_PDMA1 0x12690000
63
-
64
-
#define S5PV310_PA_GPIO1 (0x11400000)
65
-
#define S5PV310_PA_GPIO2 (0x11000000)
66
-
#define S5PV310_PA_GPIO3 (0x03860000)
67
-
68
-
#define S5PV310_PA_MIPI_CSIS0 0x11880000
69
-
#define S5PV310_PA_MIPI_CSIS1 0x11890000
70
-
71
-
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
72
-
73
-
#define S5PV310_PA_SROMC (0x12570000)
74
-
#define S5P_PA_SROMC S5PV310_PA_SROMC
75
-
76
-
/* S/PDIF */
77
-
#define S5PV310_PA_SPDIF 0xE1100000
78
-
79
-
/* I2S */
80
-
#define S5PV310_PA_I2S0 0x03830000
81
-
#define S5PV310_PA_I2S1 0xE3100000
82
-
#define S5PV310_PA_I2S2 0xE2A00000
83
-
84
-
/* PCM */
85
-
#define S5PV310_PA_PCM0 0x03840000
86
-
#define S5PV310_PA_PCM1 0x13980000
87
-
#define S5PV310_PA_PCM2 0x13990000
88
-
89
-
/* AC97 */
90
-
#define S5PV310_PA_AC97 0x139A0000
91
-
92
-
#define S5PV310_PA_UART (0x13800000)
93
-
94
-
#define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
95
-
#define S5P_PA_UART0 S5P_PA_UART(0)
96
-
#define S5P_PA_UART1 S5P_PA_UART(1)
97
-
#define S5P_PA_UART2 S5P_PA_UART(2)
98
-
#define S5P_PA_UART3 S5P_PA_UART(3)
99
-
#define S5P_PA_UART4 S5P_PA_UART(4)
100
-
101
-
#define S5P_SZ_UART SZ_256
102
-
103
-
#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
104
-
105
-
#define S5PV310_PA_TIMER (0x139D0000)
106
-
#define S5P_PA_TIMER S5PV310_PA_TIMER
107
-
108
-
#define S5PV310_PA_SDRAM (0x40000000)
109
-
#define S5P_PA_SDRAM S5PV310_PA_SDRAM
110
111
#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
112
#define S5PV310_PA_SYSMMU_SSS 0x10A50000
···
78
#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
79
#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
80
81
-
/* compatibiltiy defines. */
82
-
#define S3C_PA_UART S5PV310_PA_UART
83
#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
84
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
85
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
···
117
#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
118
#define S3C_PA_RTC S5PV310_PA_RTC
119
#define S3C_PA_WDT S5PV310_PA_WATCHDOG
120
#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
121
#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
122
123
#endif /* __ASM_ARCH_MAP_H */
···
1
/* linux/arch/arm/mach-s5pv310/include/mach/map.h
2
*
3
+
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4
* http://www.samsung.com/
5
*
6
* S5PV310 - Memory map definitions
···
23
24
#include <plat/map-s5p.h>
25
26
+
#define S5PV310_PA_SYSRAM 0x02025000
27
+
28
+
#define S5PV310_PA_I2S0 0x03830000
29
+
#define S5PV310_PA_I2S1 0xE3100000
30
+
#define S5PV310_PA_I2S2 0xE2A00000
31
+
32
+
#define S5PV310_PA_PCM0 0x03840000
33
+
#define S5PV310_PA_PCM1 0x13980000
34
+
#define S5PV310_PA_PCM2 0x13990000
35
36
#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
37
38
+
#define S5PC210_PA_ONENAND 0x0C000000
39
+
#define S5PC210_PA_ONENAND_DMA 0x0C600000
40
41
+
#define S5PV310_PA_CHIPID 0x10000000
42
43
+
#define S5PV310_PA_SYSCON 0x10010000
44
+
#define S5PV310_PA_PMU 0x10020000
45
+
#define S5PV310_PA_CMU 0x10030000
46
47
+
#define S5PV310_PA_WATCHDOG 0x10060000
48
+
#define S5PV310_PA_RTC 0x10070000
49
50
+
#define S5PV310_PA_DMC0 0x10400000
51
52
+
#define S5PV310_PA_COMBINER 0x10448000
53
54
+
#define S5PV310_PA_COREPERI 0x10500000
55
+
#define S5PV310_PA_GIC_CPU 0x10500100
56
+
#define S5PV310_PA_TWD 0x10500600
57
+
#define S5PV310_PA_GIC_DIST 0x10501000
58
+
#define S5PV310_PA_L2CC 0x10502000
59
60
+
#define S5PV310_PA_MDMA 0x10810000
61
+
#define S5PV310_PA_PDMA0 0x12680000
62
+
#define S5PV310_PA_PDMA1 0x12690000
63
64
#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
65
#define S5PV310_PA_SYSMMU_SSS 0x10A50000
···
125
#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
126
#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
127
128
+
#define S5PV310_PA_GPIO1 0x11400000
129
+
#define S5PV310_PA_GPIO2 0x11000000
130
+
#define S5PV310_PA_GPIO3 0x03860000
131
+
132
+
#define S5PV310_PA_MIPI_CSIS0 0x11880000
133
+
#define S5PV310_PA_MIPI_CSIS1 0x11890000
134
+
135
+
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
136
+
137
+
#define S5PV310_PA_SROMC 0x12570000
138
+
139
+
#define S5PV310_PA_UART 0x13800000
140
+
141
+
#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
142
+
143
+
#define S5PV310_PA_AC97 0x139A0000
144
+
145
+
#define S5PV310_PA_TIMER 0x139D0000
146
+
147
+
#define S5PV310_PA_SDRAM 0x40000000
148
+
149
+
#define S5PV310_PA_SPDIF 0xE1100000
150
+
151
+
/* Compatibiltiy Defines */
152
+
153
#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
154
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
155
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
···
141
#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
142
#define S3C_PA_RTC S5PV310_PA_RTC
143
#define S3C_PA_WDT S5PV310_PA_WATCHDOG
144
+
145
+
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
146
#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
147
#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
148
+
#define S5P_PA_ONENAND S5PC210_PA_ONENAND
149
+
#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
150
+
#define S5P_PA_SDRAM S5PV310_PA_SDRAM
151
+
#define S5P_PA_SROMC S5PV310_PA_SROMC
152
+
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
153
+
#define S5P_PA_TIMER S5PV310_PA_TIMER
154
+
155
+
/* UART */
156
+
157
+
#define S3C_PA_UART S5PV310_PA_UART
158
+
159
+
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
160
+
#define S5P_PA_UART0 S5P_PA_UART(0)
161
+
#define S5P_PA_UART1 S5P_PA_UART(1)
162
+
#define S5P_PA_UART2 S5P_PA_UART(2)
163
+
#define S5P_PA_UART3 S5P_PA_UART(3)
164
+
#define S5P_PA_UART4 S5P_PA_UART(4)
165
+
166
+
#define S5P_SZ_UART SZ_256
167
168
#endif /* __ASM_ARCH_MAP_H */
+6
-6
arch/arm/plat-s5p/dev-uart.c
+6
-6
arch/arm/plat-s5p/dev-uart.c
···
28
static struct resource s5p_uart0_resource[] = {
29
[0] = {
30
.start = S5P_PA_UART0,
31
-
.end = S5P_PA_UART0 + S5P_SZ_UART,
32
.flags = IORESOURCE_MEM,
33
},
34
[1] = {
···
51
static struct resource s5p_uart1_resource[] = {
52
[0] = {
53
.start = S5P_PA_UART1,
54
-
.end = S5P_PA_UART1 + S5P_SZ_UART,
55
.flags = IORESOURCE_MEM,
56
},
57
[1] = {
···
74
static struct resource s5p_uart2_resource[] = {
75
[0] = {
76
.start = S5P_PA_UART2,
77
-
.end = S5P_PA_UART2 + S5P_SZ_UART,
78
.flags = IORESOURCE_MEM,
79
},
80
[1] = {
···
98
#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
99
[0] = {
100
.start = S5P_PA_UART3,
101
-
.end = S5P_PA_UART3 + S5P_SZ_UART,
102
.flags = IORESOURCE_MEM,
103
},
104
[1] = {
···
123
#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
124
[0] = {
125
.start = S5P_PA_UART4,
126
-
.end = S5P_PA_UART4 + S5P_SZ_UART,
127
.flags = IORESOURCE_MEM,
128
},
129
[1] = {
···
148
#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
149
[0] = {
150
.start = S5P_PA_UART5,
151
-
.end = S5P_PA_UART5 + S5P_SZ_UART,
152
.flags = IORESOURCE_MEM,
153
},
154
[1] = {
···
28
static struct resource s5p_uart0_resource[] = {
29
[0] = {
30
.start = S5P_PA_UART0,
31
+
.end = S5P_PA_UART0 + S5P_SZ_UART - 1,
32
.flags = IORESOURCE_MEM,
33
},
34
[1] = {
···
51
static struct resource s5p_uart1_resource[] = {
52
[0] = {
53
.start = S5P_PA_UART1,
54
+
.end = S5P_PA_UART1 + S5P_SZ_UART - 1,
55
.flags = IORESOURCE_MEM,
56
},
57
[1] = {
···
74
static struct resource s5p_uart2_resource[] = {
75
[0] = {
76
.start = S5P_PA_UART2,
77
+
.end = S5P_PA_UART2 + S5P_SZ_UART - 1,
78
.flags = IORESOURCE_MEM,
79
},
80
[1] = {
···
98
#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
99
[0] = {
100
.start = S5P_PA_UART3,
101
+
.end = S5P_PA_UART3 + S5P_SZ_UART - 1,
102
.flags = IORESOURCE_MEM,
103
},
104
[1] = {
···
123
#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
124
[0] = {
125
.start = S5P_PA_UART4,
126
+
.end = S5P_PA_UART4 + S5P_SZ_UART - 1,
127
.flags = IORESOURCE_MEM,
128
},
129
[1] = {
···
148
#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
149
[0] = {
150
.start = S5P_PA_UART5,
151
+
.end = S5P_PA_UART5 + S5P_SZ_UART - 1,
152
.flags = IORESOURCE_MEM,
153
},
154
[1] = {