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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
Disintegrate asm/system.h for PowerPC
Disintegrate asm/system.h for PowerPC.
Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
cc: linuxppc-dev@lists.ozlabs.org
+687
-701
+2
-6
arch/powerpc/include/asm/atomic.h
+2
-6
arch/powerpc/include/asm/atomic.h
···
5
5
* PowerPC atomic operations
6
6
*/
7
7
8
-
#include <linux/types.h>
9
-
10
8
#ifdef __KERNEL__
11
-
#include <linux/compiler.h>
12
-
#include <asm/synch.h>
13
-
#include <asm/asm-compat.h>
14
-
#include <asm/system.h>
9
+
#include <linux/types.h>
10
+
#include <asm/cmpxchg.h>
15
11
16
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#define ATOMIC_INIT(i) { (i) }
17
13
+2
arch/powerpc/include/asm/auxvec.h
+2
arch/powerpc/include/asm/auxvec.h
+68
arch/powerpc/include/asm/barrier.h
+68
arch/powerpc/include/asm/barrier.h
···
1
+
/*
2
+
* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3
+
*/
4
+
#ifndef _ASM_POWERPC_BARRIER_H
5
+
#define _ASM_POWERPC_BARRIER_H
6
+
7
+
/*
8
+
* Memory barrier.
9
+
* The sync instruction guarantees that all memory accesses initiated
10
+
* by this processor have been performed (with respect to all other
11
+
* mechanisms that access memory). The eieio instruction is a barrier
12
+
* providing an ordering (separately) for (a) cacheable stores and (b)
13
+
* loads and stores to non-cacheable memory (e.g. I/O devices).
14
+
*
15
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* mb() prevents loads and stores being reordered across this point.
16
+
* rmb() prevents loads being reordered across this point.
17
+
* wmb() prevents stores being reordered across this point.
18
+
* read_barrier_depends() prevents data-dependent loads being reordered
19
+
* across this point (nop on PPC).
20
+
*
21
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* *mb() variants without smp_ prefix must order all types of memory
22
+
* operations with one another. sync is the only instruction sufficient
23
+
* to do this.
24
+
*
25
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* For the smp_ barriers, ordering is for cacheable memory operations
26
+
* only. We have to use the sync instruction for smp_mb(), since lwsync
27
+
* doesn't order loads with respect to previous stores. Lwsync can be
28
+
* used for smp_rmb() and smp_wmb().
29
+
*
30
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* However, on CPUs that don't support lwsync, lwsync actually maps to a
31
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* heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
32
+
*/
33
+
#define mb() __asm__ __volatile__ ("sync" : : : "memory")
34
+
#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
35
+
#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
36
+
#define read_barrier_depends() do { } while(0)
37
+
38
+
#define set_mb(var, value) do { var = value; mb(); } while (0)
39
+
40
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#ifdef CONFIG_SMP
41
+
42
+
#ifdef __SUBARCH_HAS_LWSYNC
43
+
# define SMPWMB LWSYNC
44
+
#else
45
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# define SMPWMB eieio
46
+
#endif
47
+
48
+
#define smp_mb() mb()
49
+
#define smp_rmb() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
50
+
#define smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
51
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#define smp_read_barrier_depends() read_barrier_depends()
52
+
#else
53
+
#define smp_mb() barrier()
54
+
#define smp_rmb() barrier()
55
+
#define smp_wmb() barrier()
56
+
#define smp_read_barrier_depends() do { } while(0)
57
+
#endif /* CONFIG_SMP */
58
+
59
+
/*
60
+
* This is a barrier which prevents following instructions from being
61
+
* started until the value of the argument x is known. For example, if
62
+
* x is a variable loaded from memory, this prevents following
63
+
* instructions from being executed until the load has been performed.
64
+
*/
65
+
#define data_barrier(x) \
66
+
asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
67
+
68
+
#endif /* _ASM_POWERPC_BARRIER_H */
+11
arch/powerpc/include/asm/bug.h
+11
arch/powerpc/include/asm/bug.h
···
126
126
127
127
#include <asm-generic/bug.h>
128
128
129
+
#ifndef __ASSEMBLY__
130
+
131
+
struct pt_regs;
132
+
extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
133
+
extern void bad_page_fault(struct pt_regs *, unsigned long, int);
134
+
extern void _exception(int, struct pt_regs *, int, unsigned long);
135
+
extern void die(const char *, struct pt_regs *, long);
136
+
extern void print_backtrace(unsigned long *);
137
+
138
+
#endif /* !__ASSEMBLY__ */
139
+
129
140
#endif /* __KERNEL__ */
130
141
#endif /* _ASM_POWERPC_BUG_H */
+16
arch/powerpc/include/asm/cache.h
+16
arch/powerpc/include/asm/cache.h
···
42
42
#endif /* __powerpc64__ && ! __ASSEMBLY__ */
43
43
44
44
#if !defined(__ASSEMBLY__)
45
+
45
46
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
47
+
48
+
#ifdef CONFIG_6xx
49
+
extern long _get_L2CR(void);
50
+
extern long _get_L3CR(void);
51
+
extern void _set_L2CR(unsigned long);
52
+
extern void _set_L3CR(unsigned long);
53
+
#else
54
+
#define _get_L2CR() 0L
55
+
#define _get_L3CR() 0L
56
+
#define _set_L2CR(val) do { } while(0)
57
+
#define _set_L3CR(val) do { } while(0)
46
58
#endif
47
59
60
+
extern void cacheable_memzero(void *p, unsigned int nb);
61
+
extern void *cacheable_memcpy(void *, const void *, unsigned int);
62
+
63
+
#endif /* !__ASSEMBLY__ */
48
64
#endif /* __KERNEL__ */
49
65
#endif /* _ASM_POWERPC_CACHE_H */
+309
arch/powerpc/include/asm/cmpxchg.h
+309
arch/powerpc/include/asm/cmpxchg.h
···
1
+
#ifndef _ASM_POWERPC_CMPXCHG_H_
2
+
#define _ASM_POWERPC_CMPXCHG_H_
3
+
4
+
#ifdef __KERNEL__
5
+
#include <linux/compiler.h>
6
+
#include <asm/synch.h>
7
+
#include <asm/asm-compat.h>
8
+
9
+
/*
10
+
* Atomic exchange
11
+
*
12
+
* Changes the memory location '*ptr' to be val and returns
13
+
* the previous value stored there.
14
+
*/
15
+
static __always_inline unsigned long
16
+
__xchg_u32(volatile void *p, unsigned long val)
17
+
{
18
+
unsigned long prev;
19
+
20
+
__asm__ __volatile__(
21
+
PPC_RELEASE_BARRIER
22
+
"1: lwarx %0,0,%2 \n"
23
+
PPC405_ERR77(0,%2)
24
+
" stwcx. %3,0,%2 \n\
25
+
bne- 1b"
26
+
PPC_ACQUIRE_BARRIER
27
+
: "=&r" (prev), "+m" (*(volatile unsigned int *)p)
28
+
: "r" (p), "r" (val)
29
+
: "cc", "memory");
30
+
31
+
return prev;
32
+
}
33
+
34
+
/*
35
+
* Atomic exchange
36
+
*
37
+
* Changes the memory location '*ptr' to be val and returns
38
+
* the previous value stored there.
39
+
*/
40
+
static __always_inline unsigned long
41
+
__xchg_u32_local(volatile void *p, unsigned long val)
42
+
{
43
+
unsigned long prev;
44
+
45
+
__asm__ __volatile__(
46
+
"1: lwarx %0,0,%2 \n"
47
+
PPC405_ERR77(0,%2)
48
+
" stwcx. %3,0,%2 \n\
49
+
bne- 1b"
50
+
: "=&r" (prev), "+m" (*(volatile unsigned int *)p)
51
+
: "r" (p), "r" (val)
52
+
: "cc", "memory");
53
+
54
+
return prev;
55
+
}
56
+
57
+
#ifdef CONFIG_PPC64
58
+
static __always_inline unsigned long
59
+
__xchg_u64(volatile void *p, unsigned long val)
60
+
{
61
+
unsigned long prev;
62
+
63
+
__asm__ __volatile__(
64
+
PPC_RELEASE_BARRIER
65
+
"1: ldarx %0,0,%2 \n"
66
+
PPC405_ERR77(0,%2)
67
+
" stdcx. %3,0,%2 \n\
68
+
bne- 1b"
69
+
PPC_ACQUIRE_BARRIER
70
+
: "=&r" (prev), "+m" (*(volatile unsigned long *)p)
71
+
: "r" (p), "r" (val)
72
+
: "cc", "memory");
73
+
74
+
return prev;
75
+
}
76
+
77
+
static __always_inline unsigned long
78
+
__xchg_u64_local(volatile void *p, unsigned long val)
79
+
{
80
+
unsigned long prev;
81
+
82
+
__asm__ __volatile__(
83
+
"1: ldarx %0,0,%2 \n"
84
+
PPC405_ERR77(0,%2)
85
+
" stdcx. %3,0,%2 \n\
86
+
bne- 1b"
87
+
: "=&r" (prev), "+m" (*(volatile unsigned long *)p)
88
+
: "r" (p), "r" (val)
89
+
: "cc", "memory");
90
+
91
+
return prev;
92
+
}
93
+
#endif
94
+
95
+
/*
96
+
* This function doesn't exist, so you'll get a linker error
97
+
* if something tries to do an invalid xchg().
98
+
*/
99
+
extern void __xchg_called_with_bad_pointer(void);
100
+
101
+
static __always_inline unsigned long
102
+
__xchg(volatile void *ptr, unsigned long x, unsigned int size)
103
+
{
104
+
switch (size) {
105
+
case 4:
106
+
return __xchg_u32(ptr, x);
107
+
#ifdef CONFIG_PPC64
108
+
case 8:
109
+
return __xchg_u64(ptr, x);
110
+
#endif
111
+
}
112
+
__xchg_called_with_bad_pointer();
113
+
return x;
114
+
}
115
+
116
+
static __always_inline unsigned long
117
+
__xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
118
+
{
119
+
switch (size) {
120
+
case 4:
121
+
return __xchg_u32_local(ptr, x);
122
+
#ifdef CONFIG_PPC64
123
+
case 8:
124
+
return __xchg_u64_local(ptr, x);
125
+
#endif
126
+
}
127
+
__xchg_called_with_bad_pointer();
128
+
return x;
129
+
}
130
+
#define xchg(ptr,x) \
131
+
({ \
132
+
__typeof__(*(ptr)) _x_ = (x); \
133
+
(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
134
+
})
135
+
136
+
#define xchg_local(ptr,x) \
137
+
({ \
138
+
__typeof__(*(ptr)) _x_ = (x); \
139
+
(__typeof__(*(ptr))) __xchg_local((ptr), \
140
+
(unsigned long)_x_, sizeof(*(ptr))); \
141
+
})
142
+
143
+
/*
144
+
* Compare and exchange - if *p == old, set it to new,
145
+
* and return the old value of *p.
146
+
*/
147
+
#define __HAVE_ARCH_CMPXCHG 1
148
+
149
+
static __always_inline unsigned long
150
+
__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
151
+
{
152
+
unsigned int prev;
153
+
154
+
__asm__ __volatile__ (
155
+
PPC_RELEASE_BARRIER
156
+
"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
157
+
cmpw 0,%0,%3\n\
158
+
bne- 2f\n"
159
+
PPC405_ERR77(0,%2)
160
+
" stwcx. %4,0,%2\n\
161
+
bne- 1b"
162
+
PPC_ACQUIRE_BARRIER
163
+
"\n\
164
+
2:"
165
+
: "=&r" (prev), "+m" (*p)
166
+
: "r" (p), "r" (old), "r" (new)
167
+
: "cc", "memory");
168
+
169
+
return prev;
170
+
}
171
+
172
+
static __always_inline unsigned long
173
+
__cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
174
+
unsigned long new)
175
+
{
176
+
unsigned int prev;
177
+
178
+
__asm__ __volatile__ (
179
+
"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
180
+
cmpw 0,%0,%3\n\
181
+
bne- 2f\n"
182
+
PPC405_ERR77(0,%2)
183
+
" stwcx. %4,0,%2\n\
184
+
bne- 1b"
185
+
"\n\
186
+
2:"
187
+
: "=&r" (prev), "+m" (*p)
188
+
: "r" (p), "r" (old), "r" (new)
189
+
: "cc", "memory");
190
+
191
+
return prev;
192
+
}
193
+
194
+
#ifdef CONFIG_PPC64
195
+
static __always_inline unsigned long
196
+
__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
197
+
{
198
+
unsigned long prev;
199
+
200
+
__asm__ __volatile__ (
201
+
PPC_RELEASE_BARRIER
202
+
"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
203
+
cmpd 0,%0,%3\n\
204
+
bne- 2f\n\
205
+
stdcx. %4,0,%2\n\
206
+
bne- 1b"
207
+
PPC_ACQUIRE_BARRIER
208
+
"\n\
209
+
2:"
210
+
: "=&r" (prev), "+m" (*p)
211
+
: "r" (p), "r" (old), "r" (new)
212
+
: "cc", "memory");
213
+
214
+
return prev;
215
+
}
216
+
217
+
static __always_inline unsigned long
218
+
__cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
219
+
unsigned long new)
220
+
{
221
+
unsigned long prev;
222
+
223
+
__asm__ __volatile__ (
224
+
"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
225
+
cmpd 0,%0,%3\n\
226
+
bne- 2f\n\
227
+
stdcx. %4,0,%2\n\
228
+
bne- 1b"
229
+
"\n\
230
+
2:"
231
+
: "=&r" (prev), "+m" (*p)
232
+
: "r" (p), "r" (old), "r" (new)
233
+
: "cc", "memory");
234
+
235
+
return prev;
236
+
}
237
+
#endif
238
+
239
+
/* This function doesn't exist, so you'll get a linker error
240
+
if something tries to do an invalid cmpxchg(). */
241
+
extern void __cmpxchg_called_with_bad_pointer(void);
242
+
243
+
static __always_inline unsigned long
244
+
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
245
+
unsigned int size)
246
+
{
247
+
switch (size) {
248
+
case 4:
249
+
return __cmpxchg_u32(ptr, old, new);
250
+
#ifdef CONFIG_PPC64
251
+
case 8:
252
+
return __cmpxchg_u64(ptr, old, new);
253
+
#endif
254
+
}
255
+
__cmpxchg_called_with_bad_pointer();
256
+
return old;
257
+
}
258
+
259
+
static __always_inline unsigned long
260
+
__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
261
+
unsigned int size)
262
+
{
263
+
switch (size) {
264
+
case 4:
265
+
return __cmpxchg_u32_local(ptr, old, new);
266
+
#ifdef CONFIG_PPC64
267
+
case 8:
268
+
return __cmpxchg_u64_local(ptr, old, new);
269
+
#endif
270
+
}
271
+
__cmpxchg_called_with_bad_pointer();
272
+
return old;
273
+
}
274
+
275
+
#define cmpxchg(ptr, o, n) \
276
+
({ \
277
+
__typeof__(*(ptr)) _o_ = (o); \
278
+
__typeof__(*(ptr)) _n_ = (n); \
279
+
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
280
+
(unsigned long)_n_, sizeof(*(ptr))); \
281
+
})
282
+
283
+
284
+
#define cmpxchg_local(ptr, o, n) \
285
+
({ \
286
+
__typeof__(*(ptr)) _o_ = (o); \
287
+
__typeof__(*(ptr)) _n_ = (n); \
288
+
(__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
289
+
(unsigned long)_n_, sizeof(*(ptr))); \
290
+
})
291
+
292
+
#ifdef CONFIG_PPC64
293
+
#define cmpxchg64(ptr, o, n) \
294
+
({ \
295
+
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
296
+
cmpxchg((ptr), (o), (n)); \
297
+
})
298
+
#define cmpxchg64_local(ptr, o, n) \
299
+
({ \
300
+
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
301
+
cmpxchg_local((ptr), (o), (n)); \
302
+
})
303
+
#else
304
+
#include <asm-generic/cmpxchg-local.h>
305
+
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
306
+
#endif
307
+
308
+
#endif /* __KERNEL__ */
309
+
#endif /* _ASM_POWERPC_CMPXCHG_H_ */
+56
arch/powerpc/include/asm/debug.h
+56
arch/powerpc/include/asm/debug.h
···
1
+
/*
2
+
* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3
+
*/
4
+
#ifndef _ASM_POWERPC_DEBUG_H
5
+
#define _ASM_POWERPC_DEBUG_H
6
+
7
+
struct pt_regs;
8
+
9
+
extern struct dentry *powerpc_debugfs_root;
10
+
11
+
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
12
+
13
+
extern int (*__debugger)(struct pt_regs *regs);
14
+
extern int (*__debugger_ipi)(struct pt_regs *regs);
15
+
extern int (*__debugger_bpt)(struct pt_regs *regs);
16
+
extern int (*__debugger_sstep)(struct pt_regs *regs);
17
+
extern int (*__debugger_iabr_match)(struct pt_regs *regs);
18
+
extern int (*__debugger_dabr_match)(struct pt_regs *regs);
19
+
extern int (*__debugger_fault_handler)(struct pt_regs *regs);
20
+
21
+
#define DEBUGGER_BOILERPLATE(__NAME) \
22
+
static inline int __NAME(struct pt_regs *regs) \
23
+
{ \
24
+
if (unlikely(__ ## __NAME)) \
25
+
return __ ## __NAME(regs); \
26
+
return 0; \
27
+
}
28
+
29
+
DEBUGGER_BOILERPLATE(debugger)
30
+
DEBUGGER_BOILERPLATE(debugger_ipi)
31
+
DEBUGGER_BOILERPLATE(debugger_bpt)
32
+
DEBUGGER_BOILERPLATE(debugger_sstep)
33
+
DEBUGGER_BOILERPLATE(debugger_iabr_match)
34
+
DEBUGGER_BOILERPLATE(debugger_dabr_match)
35
+
DEBUGGER_BOILERPLATE(debugger_fault_handler)
36
+
37
+
#else
38
+
static inline int debugger(struct pt_regs *regs) { return 0; }
39
+
static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
40
+
static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
41
+
static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
42
+
static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
43
+
static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
44
+
static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
45
+
#endif
46
+
47
+
extern int set_dabr(unsigned long dabr);
48
+
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
49
+
extern void do_send_trap(struct pt_regs *regs, unsigned long address,
50
+
unsigned long error_code, int signal_code, int brkpt);
51
+
#else
52
+
extern void do_dabr(struct pt_regs *regs, unsigned long address,
53
+
unsigned long error_code);
54
+
#endif
55
+
56
+
#endif /* _ASM_POWERPC_DEBUG_H */
-1
arch/powerpc/include/asm/dma.h
-1
arch/powerpc/include/asm/dma.h
+9
arch/powerpc/include/asm/exec.h
+9
arch/powerpc/include/asm/exec.h
+1
-1
arch/powerpc/include/asm/hw_breakpoint.h
+1
-1
arch/powerpc/include/asm/hw_breakpoint.h
+30
arch/powerpc/include/asm/processor.h
+30
arch/powerpc/include/asm/processor.h
···
385
385
extern unsigned long cpuidle_disable;
386
386
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
387
387
388
+
extern int powersave_nap; /* set if nap mode can be used in idle loop */
389
+
void cpu_idle_wait(void);
390
+
391
+
#ifdef CONFIG_PSERIES_IDLE
392
+
extern void update_smt_snooze_delay(int snooze);
393
+
extern int pseries_notify_cpuidle_add_cpu(int cpu);
394
+
#else
395
+
static inline void update_smt_snooze_delay(int snooze) {}
396
+
static inline int pseries_notify_cpuidle_add_cpu(int cpu) { return 0; }
397
+
#endif
398
+
399
+
extern void flush_instruction_cache(void);
400
+
extern void hard_reset_now(void);
401
+
extern void poweroff_now(void);
402
+
extern int fix_alignment(struct pt_regs *);
403
+
extern void cvt_fd(float *from, double *to);
404
+
extern void cvt_df(double *from, float *to);
405
+
extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
406
+
407
+
#ifdef CONFIG_PPC64
408
+
/*
409
+
* We handle most unaligned accesses in hardware. On the other hand
410
+
* unaligned DMA can be very expensive on some ppc64 IO chips (it does
411
+
* powers of 2 writes until it reaches sufficient alignment).
412
+
*
413
+
* Based on this we disable the IP header alignment in network drivers.
414
+
*/
415
+
#define NET_IP_ALIGN 0
416
+
#endif
417
+
388
418
#endif /* __KERNEL__ */
389
419
#endif /* __ASSEMBLY__ */
390
420
#endif /* _ASM_POWERPC_PROCESSOR_H */
+5
arch/powerpc/include/asm/reg_booke.h
+5
arch/powerpc/include/asm/reg_booke.h
···
15
15
#ifndef __ASM_POWERPC_REG_BOOKE_H__
16
16
#define __ASM_POWERPC_REG_BOOKE_H__
17
17
18
+
#ifdef CONFIG_BOOKE_WDT
19
+
extern u32 booke_wdt_enabled;
20
+
extern u32 booke_wdt_period;
21
+
#endif /* CONFIG_BOOKE_WDT */
22
+
18
23
/* Machine State Register (MSR) Fields */
19
24
#define MSR_GS (1<<28) /* Guest state */
20
25
#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
+2
arch/powerpc/include/asm/rtas.h
+2
arch/powerpc/include/asm/rtas.h
+45
arch/powerpc/include/asm/runlatch.h
+45
arch/powerpc/include/asm/runlatch.h
···
1
+
/*
2
+
* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3
+
*/
4
+
#ifndef _ASM_POWERPC_RUNLATCH_H
5
+
#define _ASM_POWERPC_RUNLATCH_H
6
+
7
+
#ifdef CONFIG_PPC64
8
+
9
+
extern void __ppc64_runlatch_on(void);
10
+
extern void __ppc64_runlatch_off(void);
11
+
12
+
/*
13
+
* We manually hard enable-disable, this is called
14
+
* in the idle loop and we don't want to mess up
15
+
* with soft-disable/enable & interrupt replay.
16
+
*/
17
+
#define ppc64_runlatch_off() \
18
+
do { \
19
+
if (cpu_has_feature(CPU_FTR_CTRL) && \
20
+
test_thread_local_flags(_TLF_RUNLATCH)) { \
21
+
unsigned long msr = mfmsr(); \
22
+
__hard_irq_disable(); \
23
+
__ppc64_runlatch_off(); \
24
+
if (msr & MSR_EE) \
25
+
__hard_irq_enable(); \
26
+
} \
27
+
} while (0)
28
+
29
+
#define ppc64_runlatch_on() \
30
+
do { \
31
+
if (cpu_has_feature(CPU_FTR_CTRL) && \
32
+
!test_thread_local_flags(_TLF_RUNLATCH)) { \
33
+
unsigned long msr = mfmsr(); \
34
+
__hard_irq_disable(); \
35
+
__ppc64_runlatch_on(); \
36
+
if (msr & MSR_EE) \
37
+
__hard_irq_enable(); \
38
+
} \
39
+
} while (0)
40
+
#else
41
+
#define ppc64_runlatch_on()
42
+
#define ppc64_runlatch_off()
43
+
#endif /* CONFIG_PPC64 */
44
+
45
+
#endif /* _ASM_POWERPC_RUNLATCH_H */
+23
-1
arch/powerpc/include/asm/setup.h
+23
-1
arch/powerpc/include/asm/setup.h
···
5
5
6
6
#ifndef __ASSEMBLY__
7
7
extern void ppc_printk_progress(char *s, unsigned short hex);
8
-
#endif
8
+
9
+
extern unsigned int rtas_data;
10
+
extern int mem_init_done; /* set on boot once kmalloc can be called */
11
+
extern int init_bootmem_done; /* set once bootmem is available */
12
+
extern phys_addr_t memory_limit;
13
+
extern unsigned long klimit;
14
+
extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
15
+
16
+
extern void via_cuda_init(void);
17
+
extern void read_rtc_time(void);
18
+
extern void pmac_find_display(void);
19
+
20
+
struct device_node;
21
+
extern void note_scsi_host(struct device_node *, void *);
22
+
23
+
/* Used in very early kernel initialization. */
24
+
extern unsigned long reloc_offset(void);
25
+
extern unsigned long add_reloc_offset(unsigned long);
26
+
extern void reloc_got2(unsigned long);
27
+
28
+
#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
29
+
30
+
#endif /* !__ASSEMBLY__ */
9
31
10
32
#endif /* _ASM_POWERPC_SETUP_H */
+65
arch/powerpc/include/asm/switch_to.h
+65
arch/powerpc/include/asm/switch_to.h
···
1
+
/*
2
+
* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3
+
*/
4
+
#ifndef _ASM_POWERPC_SWITCH_TO_H
5
+
#define _ASM_POWERPC_SWITCH_TO_H
6
+
7
+
struct thread_struct;
8
+
struct task_struct;
9
+
struct pt_regs;
10
+
11
+
extern struct task_struct *__switch_to(struct task_struct *,
12
+
struct task_struct *);
13
+
#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
14
+
15
+
struct thread_struct;
16
+
extern struct task_struct *_switch(struct thread_struct *prev,
17
+
struct thread_struct *next);
18
+
19
+
extern void giveup_fpu(struct task_struct *);
20
+
extern void disable_kernel_fp(void);
21
+
extern void enable_kernel_fp(void);
22
+
extern void flush_fp_to_thread(struct task_struct *);
23
+
extern void enable_kernel_altivec(void);
24
+
extern void giveup_altivec(struct task_struct *);
25
+
extern void load_up_altivec(struct task_struct *);
26
+
extern int emulate_altivec(struct pt_regs *);
27
+
extern void __giveup_vsx(struct task_struct *);
28
+
extern void giveup_vsx(struct task_struct *);
29
+
extern void enable_kernel_spe(void);
30
+
extern void giveup_spe(struct task_struct *);
31
+
extern void load_up_spe(struct task_struct *);
32
+
33
+
#ifndef CONFIG_SMP
34
+
extern void discard_lazy_cpu_state(void);
35
+
#else
36
+
static inline void discard_lazy_cpu_state(void)
37
+
{
38
+
}
39
+
#endif
40
+
41
+
#ifdef CONFIG_ALTIVEC
42
+
extern void flush_altivec_to_thread(struct task_struct *);
43
+
#else
44
+
static inline void flush_altivec_to_thread(struct task_struct *t)
45
+
{
46
+
}
47
+
#endif
48
+
49
+
#ifdef CONFIG_VSX
50
+
extern void flush_vsx_to_thread(struct task_struct *);
51
+
#else
52
+
static inline void flush_vsx_to_thread(struct task_struct *t)
53
+
{
54
+
}
55
+
#endif
56
+
57
+
#ifdef CONFIG_SPE
58
+
extern void flush_spe_to_thread(struct task_struct *);
59
+
#else
60
+
static inline void flush_spe_to_thread(struct task_struct *t)
61
+
{
62
+
}
63
+
#endif
64
+
65
+
#endif /* _ASM_POWERPC_SWITCH_TO_H */
+6
-592
arch/powerpc/include/asm/system.h
+6
-592
arch/powerpc/include/asm/system.h
···
1
-
/*
2
-
* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3
-
*/
4
-
#ifndef _ASM_POWERPC_SYSTEM_H
5
-
#define _ASM_POWERPC_SYSTEM_H
6
-
7
-
#include <linux/kernel.h>
8
-
#include <linux/irqflags.h>
9
-
10
-
#include <asm/hw_irq.h>
11
-
12
-
/*
13
-
* Memory barrier.
14
-
* The sync instruction guarantees that all memory accesses initiated
15
-
* by this processor have been performed (with respect to all other
16
-
* mechanisms that access memory). The eieio instruction is a barrier
17
-
* providing an ordering (separately) for (a) cacheable stores and (b)
18
-
* loads and stores to non-cacheable memory (e.g. I/O devices).
19
-
*
20
-
* mb() prevents loads and stores being reordered across this point.
21
-
* rmb() prevents loads being reordered across this point.
22
-
* wmb() prevents stores being reordered across this point.
23
-
* read_barrier_depends() prevents data-dependent loads being reordered
24
-
* across this point (nop on PPC).
25
-
*
26
-
* *mb() variants without smp_ prefix must order all types of memory
27
-
* operations with one another. sync is the only instruction sufficient
28
-
* to do this.
29
-
*
30
-
* For the smp_ barriers, ordering is for cacheable memory operations
31
-
* only. We have to use the sync instruction for smp_mb(), since lwsync
32
-
* doesn't order loads with respect to previous stores. Lwsync can be
33
-
* used for smp_rmb() and smp_wmb().
34
-
*
35
-
* However, on CPUs that don't support lwsync, lwsync actually maps to a
36
-
* heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
37
-
*/
38
-
#define mb() __asm__ __volatile__ ("sync" : : : "memory")
39
-
#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
40
-
#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
41
-
#define read_barrier_depends() do { } while(0)
42
-
43
-
#define set_mb(var, value) do { var = value; mb(); } while (0)
44
-
45
-
#ifdef __KERNEL__
46
-
#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
47
-
#ifdef CONFIG_SMP
48
-
49
-
#ifdef __SUBARCH_HAS_LWSYNC
50
-
# define SMPWMB LWSYNC
51
-
#else
52
-
# define SMPWMB eieio
53
-
#endif
54
-
55
-
#define smp_mb() mb()
56
-
#define smp_rmb() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
57
-
#define smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
58
-
#define smp_read_barrier_depends() read_barrier_depends()
59
-
#else
60
-
#define smp_mb() barrier()
61
-
#define smp_rmb() barrier()
62
-
#define smp_wmb() barrier()
63
-
#define smp_read_barrier_depends() do { } while(0)
64
-
#endif /* CONFIG_SMP */
65
-
66
-
/*
67
-
* This is a barrier which prevents following instructions from being
68
-
* started until the value of the argument x is known. For example, if
69
-
* x is a variable loaded from memory, this prevents following
70
-
* instructions from being executed until the load has been performed.
71
-
*/
72
-
#define data_barrier(x) \
73
-
asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
74
-
75
-
struct task_struct;
76
-
struct pt_regs;
77
-
78
-
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
79
-
80
-
extern int (*__debugger)(struct pt_regs *regs);
81
-
extern int (*__debugger_ipi)(struct pt_regs *regs);
82
-
extern int (*__debugger_bpt)(struct pt_regs *regs);
83
-
extern int (*__debugger_sstep)(struct pt_regs *regs);
84
-
extern int (*__debugger_iabr_match)(struct pt_regs *regs);
85
-
extern int (*__debugger_dabr_match)(struct pt_regs *regs);
86
-
extern int (*__debugger_fault_handler)(struct pt_regs *regs);
87
-
88
-
#define DEBUGGER_BOILERPLATE(__NAME) \
89
-
static inline int __NAME(struct pt_regs *regs) \
90
-
{ \
91
-
if (unlikely(__ ## __NAME)) \
92
-
return __ ## __NAME(regs); \
93
-
return 0; \
94
-
}
95
-
96
-
DEBUGGER_BOILERPLATE(debugger)
97
-
DEBUGGER_BOILERPLATE(debugger_ipi)
98
-
DEBUGGER_BOILERPLATE(debugger_bpt)
99
-
DEBUGGER_BOILERPLATE(debugger_sstep)
100
-
DEBUGGER_BOILERPLATE(debugger_iabr_match)
101
-
DEBUGGER_BOILERPLATE(debugger_dabr_match)
102
-
DEBUGGER_BOILERPLATE(debugger_fault_handler)
103
-
104
-
#else
105
-
static inline int debugger(struct pt_regs *regs) { return 0; }
106
-
static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
107
-
static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
108
-
static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
109
-
static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
110
-
static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
111
-
static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
112
-
#endif
113
-
114
-
extern int set_dabr(unsigned long dabr);
115
-
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
116
-
extern void do_send_trap(struct pt_regs *regs, unsigned long address,
117
-
unsigned long error_code, int signal_code, int brkpt);
118
-
#else
119
-
extern void do_dabr(struct pt_regs *regs, unsigned long address,
120
-
unsigned long error_code);
121
-
#endif
122
-
extern void print_backtrace(unsigned long *);
123
-
extern void flush_instruction_cache(void);
124
-
extern void hard_reset_now(void);
125
-
extern void poweroff_now(void);
126
-
127
-
#ifdef CONFIG_6xx
128
-
extern long _get_L2CR(void);
129
-
extern long _get_L3CR(void);
130
-
extern void _set_L2CR(unsigned long);
131
-
extern void _set_L3CR(unsigned long);
132
-
#else
133
-
#define _get_L2CR() 0L
134
-
#define _get_L3CR() 0L
135
-
#define _set_L2CR(val) do { } while(0)
136
-
#define _set_L3CR(val) do { } while(0)
137
-
#endif
138
-
139
-
extern void via_cuda_init(void);
140
-
extern void read_rtc_time(void);
141
-
extern void pmac_find_display(void);
142
-
extern void giveup_fpu(struct task_struct *);
143
-
extern void disable_kernel_fp(void);
144
-
extern void enable_kernel_fp(void);
145
-
extern void flush_fp_to_thread(struct task_struct *);
146
-
extern void enable_kernel_altivec(void);
147
-
extern void giveup_altivec(struct task_struct *);
148
-
extern void load_up_altivec(struct task_struct *);
149
-
extern int emulate_altivec(struct pt_regs *);
150
-
extern void __giveup_vsx(struct task_struct *);
151
-
extern void giveup_vsx(struct task_struct *);
152
-
extern void enable_kernel_spe(void);
153
-
extern void giveup_spe(struct task_struct *);
154
-
extern void load_up_spe(struct task_struct *);
155
-
extern int fix_alignment(struct pt_regs *);
156
-
extern void cvt_fd(float *from, double *to);
157
-
extern void cvt_df(double *from, float *to);
158
-
159
-
#ifndef CONFIG_SMP
160
-
extern void discard_lazy_cpu_state(void);
161
-
#else
162
-
static inline void discard_lazy_cpu_state(void)
163
-
{
164
-
}
165
-
#endif
166
-
167
-
#ifdef CONFIG_ALTIVEC
168
-
extern void flush_altivec_to_thread(struct task_struct *);
169
-
#else
170
-
static inline void flush_altivec_to_thread(struct task_struct *t)
171
-
{
172
-
}
173
-
#endif
174
-
175
-
#ifdef CONFIG_VSX
176
-
extern void flush_vsx_to_thread(struct task_struct *);
177
-
#else
178
-
static inline void flush_vsx_to_thread(struct task_struct *t)
179
-
{
180
-
}
181
-
#endif
182
-
183
-
#ifdef CONFIG_SPE
184
-
extern void flush_spe_to_thread(struct task_struct *);
185
-
#else
186
-
static inline void flush_spe_to_thread(struct task_struct *t)
187
-
{
188
-
}
189
-
#endif
190
-
191
-
extern int call_rtas(const char *, int, int, unsigned long *, ...);
192
-
extern void cacheable_memzero(void *p, unsigned int nb);
193
-
extern void *cacheable_memcpy(void *, const void *, unsigned int);
194
-
extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
195
-
extern void bad_page_fault(struct pt_regs *, unsigned long, int);
196
-
extern void _exception(int, struct pt_regs *, int, unsigned long);
197
-
extern void die(const char *, struct pt_regs *, long);
198
-
extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
199
-
200
-
#ifdef CONFIG_BOOKE_WDT
201
-
extern u32 booke_wdt_enabled;
202
-
extern u32 booke_wdt_period;
203
-
#endif /* CONFIG_BOOKE_WDT */
204
-
205
-
struct device_node;
206
-
extern void note_scsi_host(struct device_node *, void *);
207
-
208
-
extern struct task_struct *__switch_to(struct task_struct *,
209
-
struct task_struct *);
210
-
#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
211
-
212
-
struct thread_struct;
213
-
extern struct task_struct *_switch(struct thread_struct *prev,
214
-
struct thread_struct *next);
215
-
216
-
extern unsigned int rtas_data;
217
-
extern int mem_init_done; /* set on boot once kmalloc can be called */
218
-
extern int init_bootmem_done; /* set once bootmem is available */
219
-
extern phys_addr_t memory_limit;
220
-
extern unsigned long klimit;
221
-
extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
222
-
223
-
extern int powersave_nap; /* set if nap mode can be used in idle loop */
224
-
void cpu_idle_wait(void);
225
-
226
-
#ifdef CONFIG_PSERIES_IDLE
227
-
extern void update_smt_snooze_delay(int snooze);
228
-
extern int pseries_notify_cpuidle_add_cpu(int cpu);
229
-
#else
230
-
static inline void update_smt_snooze_delay(int snooze) {}
231
-
static inline int pseries_notify_cpuidle_add_cpu(int cpu) { return 0; }
232
-
#endif
233
-
234
-
/*
235
-
* Atomic exchange
236
-
*
237
-
* Changes the memory location '*ptr' to be val and returns
238
-
* the previous value stored there.
239
-
*/
240
-
static __always_inline unsigned long
241
-
__xchg_u32(volatile void *p, unsigned long val)
242
-
{
243
-
unsigned long prev;
244
-
245
-
__asm__ __volatile__(
246
-
PPC_RELEASE_BARRIER
247
-
"1: lwarx %0,0,%2 \n"
248
-
PPC405_ERR77(0,%2)
249
-
" stwcx. %3,0,%2 \n\
250
-
bne- 1b"
251
-
PPC_ACQUIRE_BARRIER
252
-
: "=&r" (prev), "+m" (*(volatile unsigned int *)p)
253
-
: "r" (p), "r" (val)
254
-
: "cc", "memory");
255
-
256
-
return prev;
257
-
}
258
-
259
-
/*
260
-
* Atomic exchange
261
-
*
262
-
* Changes the memory location '*ptr' to be val and returns
263
-
* the previous value stored there.
264
-
*/
265
-
static __always_inline unsigned long
266
-
__xchg_u32_local(volatile void *p, unsigned long val)
267
-
{
268
-
unsigned long prev;
269
-
270
-
__asm__ __volatile__(
271
-
"1: lwarx %0,0,%2 \n"
272
-
PPC405_ERR77(0,%2)
273
-
" stwcx. %3,0,%2 \n\
274
-
bne- 1b"
275
-
: "=&r" (prev), "+m" (*(volatile unsigned int *)p)
276
-
: "r" (p), "r" (val)
277
-
: "cc", "memory");
278
-
279
-
return prev;
280
-
}
281
-
282
-
#ifdef CONFIG_PPC64
283
-
static __always_inline unsigned long
284
-
__xchg_u64(volatile void *p, unsigned long val)
285
-
{
286
-
unsigned long prev;
287
-
288
-
__asm__ __volatile__(
289
-
PPC_RELEASE_BARRIER
290
-
"1: ldarx %0,0,%2 \n"
291
-
PPC405_ERR77(0,%2)
292
-
" stdcx. %3,0,%2 \n\
293
-
bne- 1b"
294
-
PPC_ACQUIRE_BARRIER
295
-
: "=&r" (prev), "+m" (*(volatile unsigned long *)p)
296
-
: "r" (p), "r" (val)
297
-
: "cc", "memory");
298
-
299
-
return prev;
300
-
}
301
-
302
-
static __always_inline unsigned long
303
-
__xchg_u64_local(volatile void *p, unsigned long val)
304
-
{
305
-
unsigned long prev;
306
-
307
-
__asm__ __volatile__(
308
-
"1: ldarx %0,0,%2 \n"
309
-
PPC405_ERR77(0,%2)
310
-
" stdcx. %3,0,%2 \n\
311
-
bne- 1b"
312
-
: "=&r" (prev), "+m" (*(volatile unsigned long *)p)
313
-
: "r" (p), "r" (val)
314
-
: "cc", "memory");
315
-
316
-
return prev;
317
-
}
318
-
#endif
319
-
320
-
/*
321
-
* This function doesn't exist, so you'll get a linker error
322
-
* if something tries to do an invalid xchg().
323
-
*/
324
-
extern void __xchg_called_with_bad_pointer(void);
325
-
326
-
static __always_inline unsigned long
327
-
__xchg(volatile void *ptr, unsigned long x, unsigned int size)
328
-
{
329
-
switch (size) {
330
-
case 4:
331
-
return __xchg_u32(ptr, x);
332
-
#ifdef CONFIG_PPC64
333
-
case 8:
334
-
return __xchg_u64(ptr, x);
335
-
#endif
336
-
}
337
-
__xchg_called_with_bad_pointer();
338
-
return x;
339
-
}
340
-
341
-
static __always_inline unsigned long
342
-
__xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
343
-
{
344
-
switch (size) {
345
-
case 4:
346
-
return __xchg_u32_local(ptr, x);
347
-
#ifdef CONFIG_PPC64
348
-
case 8:
349
-
return __xchg_u64_local(ptr, x);
350
-
#endif
351
-
}
352
-
__xchg_called_with_bad_pointer();
353
-
return x;
354
-
}
355
-
#define xchg(ptr,x) \
356
-
({ \
357
-
__typeof__(*(ptr)) _x_ = (x); \
358
-
(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
359
-
})
360
-
361
-
#define xchg_local(ptr,x) \
362
-
({ \
363
-
__typeof__(*(ptr)) _x_ = (x); \
364
-
(__typeof__(*(ptr))) __xchg_local((ptr), \
365
-
(unsigned long)_x_, sizeof(*(ptr))); \
366
-
})
367
-
368
-
/*
369
-
* Compare and exchange - if *p == old, set it to new,
370
-
* and return the old value of *p.
371
-
*/
372
-
#define __HAVE_ARCH_CMPXCHG 1
373
-
374
-
static __always_inline unsigned long
375
-
__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
376
-
{
377
-
unsigned int prev;
378
-
379
-
__asm__ __volatile__ (
380
-
PPC_RELEASE_BARRIER
381
-
"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
382
-
cmpw 0,%0,%3\n\
383
-
bne- 2f\n"
384
-
PPC405_ERR77(0,%2)
385
-
" stwcx. %4,0,%2\n\
386
-
bne- 1b"
387
-
PPC_ACQUIRE_BARRIER
388
-
"\n\
389
-
2:"
390
-
: "=&r" (prev), "+m" (*p)
391
-
: "r" (p), "r" (old), "r" (new)
392
-
: "cc", "memory");
393
-
394
-
return prev;
395
-
}
396
-
397
-
static __always_inline unsigned long
398
-
__cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
399
-
unsigned long new)
400
-
{
401
-
unsigned int prev;
402
-
403
-
__asm__ __volatile__ (
404
-
"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
405
-
cmpw 0,%0,%3\n\
406
-
bne- 2f\n"
407
-
PPC405_ERR77(0,%2)
408
-
" stwcx. %4,0,%2\n\
409
-
bne- 1b"
410
-
"\n\
411
-
2:"
412
-
: "=&r" (prev), "+m" (*p)
413
-
: "r" (p), "r" (old), "r" (new)
414
-
: "cc", "memory");
415
-
416
-
return prev;
417
-
}
418
-
419
-
#ifdef CONFIG_PPC64
420
-
static __always_inline unsigned long
421
-
__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
422
-
{
423
-
unsigned long prev;
424
-
425
-
__asm__ __volatile__ (
426
-
PPC_RELEASE_BARRIER
427
-
"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
428
-
cmpd 0,%0,%3\n\
429
-
bne- 2f\n\
430
-
stdcx. %4,0,%2\n\
431
-
bne- 1b"
432
-
PPC_ACQUIRE_BARRIER
433
-
"\n\
434
-
2:"
435
-
: "=&r" (prev), "+m" (*p)
436
-
: "r" (p), "r" (old), "r" (new)
437
-
: "cc", "memory");
438
-
439
-
return prev;
440
-
}
441
-
442
-
static __always_inline unsigned long
443
-
__cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
444
-
unsigned long new)
445
-
{
446
-
unsigned long prev;
447
-
448
-
__asm__ __volatile__ (
449
-
"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
450
-
cmpd 0,%0,%3\n\
451
-
bne- 2f\n\
452
-
stdcx. %4,0,%2\n\
453
-
bne- 1b"
454
-
"\n\
455
-
2:"
456
-
: "=&r" (prev), "+m" (*p)
457
-
: "r" (p), "r" (old), "r" (new)
458
-
: "cc", "memory");
459
-
460
-
return prev;
461
-
}
462
-
#endif
463
-
464
-
/* This function doesn't exist, so you'll get a linker error
465
-
if something tries to do an invalid cmpxchg(). */
466
-
extern void __cmpxchg_called_with_bad_pointer(void);
467
-
468
-
static __always_inline unsigned long
469
-
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
470
-
unsigned int size)
471
-
{
472
-
switch (size) {
473
-
case 4:
474
-
return __cmpxchg_u32(ptr, old, new);
475
-
#ifdef CONFIG_PPC64
476
-
case 8:
477
-
return __cmpxchg_u64(ptr, old, new);
478
-
#endif
479
-
}
480
-
__cmpxchg_called_with_bad_pointer();
481
-
return old;
482
-
}
483
-
484
-
static __always_inline unsigned long
485
-
__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
486
-
unsigned int size)
487
-
{
488
-
switch (size) {
489
-
case 4:
490
-
return __cmpxchg_u32_local(ptr, old, new);
491
-
#ifdef CONFIG_PPC64
492
-
case 8:
493
-
return __cmpxchg_u64_local(ptr, old, new);
494
-
#endif
495
-
}
496
-
__cmpxchg_called_with_bad_pointer();
497
-
return old;
498
-
}
499
-
500
-
#define cmpxchg(ptr, o, n) \
501
-
({ \
502
-
__typeof__(*(ptr)) _o_ = (o); \
503
-
__typeof__(*(ptr)) _n_ = (n); \
504
-
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
505
-
(unsigned long)_n_, sizeof(*(ptr))); \
506
-
})
507
-
508
-
509
-
#define cmpxchg_local(ptr, o, n) \
510
-
({ \
511
-
__typeof__(*(ptr)) _o_ = (o); \
512
-
__typeof__(*(ptr)) _n_ = (n); \
513
-
(__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
514
-
(unsigned long)_n_, sizeof(*(ptr))); \
515
-
})
516
-
517
-
#ifdef CONFIG_PPC64
518
-
/*
519
-
* We handle most unaligned accesses in hardware. On the other hand
520
-
* unaligned DMA can be very expensive on some ppc64 IO chips (it does
521
-
* powers of 2 writes until it reaches sufficient alignment).
522
-
*
523
-
* Based on this we disable the IP header alignment in network drivers.
524
-
*/
525
-
#define NET_IP_ALIGN 0
526
-
527
-
#define cmpxchg64(ptr, o, n) \
528
-
({ \
529
-
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
530
-
cmpxchg((ptr), (o), (n)); \
531
-
})
532
-
#define cmpxchg64_local(ptr, o, n) \
533
-
({ \
534
-
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
535
-
cmpxchg_local((ptr), (o), (n)); \
536
-
})
537
-
#else
538
-
#include <asm-generic/cmpxchg-local.h>
539
-
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
540
-
#endif
541
-
542
-
extern unsigned long arch_align_stack(unsigned long sp);
543
-
544
-
/* Used in very early kernel initialization. */
545
-
extern unsigned long reloc_offset(void);
546
-
extern unsigned long add_reloc_offset(unsigned long);
547
-
extern void reloc_got2(unsigned long);
548
-
549
-
#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
550
-
551
-
extern struct dentry *powerpc_debugfs_root;
552
-
553
-
#ifdef CONFIG_PPC64
554
-
555
-
extern void __ppc64_runlatch_on(void);
556
-
extern void __ppc64_runlatch_off(void);
557
-
558
-
/*
559
-
* We manually hard enable-disable, this is called
560
-
* in the idle loop and we don't want to mess up
561
-
* with soft-disable/enable & interrupt replay.
562
-
*/
563
-
#define ppc64_runlatch_off() \
564
-
do { \
565
-
if (cpu_has_feature(CPU_FTR_CTRL) && \
566
-
test_thread_local_flags(_TLF_RUNLATCH)) { \
567
-
unsigned long msr = mfmsr(); \
568
-
__hard_irq_disable(); \
569
-
__ppc64_runlatch_off(); \
570
-
if (msr & MSR_EE) \
571
-
__hard_irq_enable(); \
572
-
} \
573
-
} while (0)
574
-
575
-
#define ppc64_runlatch_on() \
576
-
do { \
577
-
if (cpu_has_feature(CPU_FTR_CTRL) && \
578
-
!test_thread_local_flags(_TLF_RUNLATCH)) { \
579
-
unsigned long msr = mfmsr(); \
580
-
__hard_irq_disable(); \
581
-
__ppc64_runlatch_on(); \
582
-
if (msr & MSR_EE) \
583
-
__hard_irq_enable(); \
584
-
} \
585
-
} while (0)
586
-
#else
587
-
#define ppc64_runlatch_on()
588
-
#define ppc64_runlatch_off()
589
-
#endif /* CONFIG_PPC64 */
590
-
591
-
#endif /* __KERNEL__ */
592
-
#endif /* _ASM_POWERPC_SYSTEM_H */
1
+
/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
2
+
#include <asm/barrier.h>
3
+
#include <asm/cmpxchg.h>
4
+
#include <asm/debug.h>
5
+
#include <asm/exec.h>
6
+
#include <asm/switch_to.h>
+1
-1
arch/powerpc/kernel/align.c
+1
-1
arch/powerpc/kernel/align.c
···
21
21
#include <linux/mm.h>
22
22
#include <asm/processor.h>
23
23
#include <asm/uaccess.h>
24
-
#include <asm/system.h>
25
24
#include <asm/cache.h>
26
25
#include <asm/cputable.h>
27
26
#include <asm/emulated_ops.h>
27
+
#include <asm/switch_to.h>
28
28
29
29
struct aligninfo {
30
30
unsigned char len;
+1
arch/powerpc/kernel/cputable.c
+1
arch/powerpc/kernel/cputable.c
+1
-1
arch/powerpc/kernel/crash.c
+1
-1
arch/powerpc/kernel/crash.c
+1
-1
arch/powerpc/kernel/idle.c
+1
-1
arch/powerpc/kernel/idle.c
···
26
26
#include <linux/sysctl.h>
27
27
#include <linux/tick.h>
28
28
29
-
#include <asm/system.h>
30
29
#include <asm/processor.h>
31
30
#include <asm/cputable.h>
32
31
#include <asm/time.h>
33
32
#include <asm/machdep.h>
33
+
#include <asm/runlatch.h>
34
34
#include <asm/smp.h>
35
35
36
36
#ifdef CONFIG_HOTPLUG_CPU
+1
-1
arch/powerpc/kernel/irq.c
+1
-1
arch/powerpc/kernel/irq.c
···
57
57
#include <linux/of_irq.h>
58
58
59
59
#include <asm/uaccess.h>
60
-
#include <asm/system.h>
61
60
#include <asm/io.h>
62
61
#include <asm/pgtable.h>
63
62
#include <asm/irq.h>
···
66
67
#include <asm/machdep.h>
67
68
#include <asm/udbg.h>
68
69
#include <asm/smp.h>
70
+
#include <asm/debug.h>
69
71
70
72
#ifdef CONFIG_PPC64
71
73
#include <asm/paca.h>
-1
arch/powerpc/kernel/kprobes.c
-1
arch/powerpc/kernel/kprobes.c
-1
arch/powerpc/kernel/lparcfg.c
-1
arch/powerpc/kernel/lparcfg.c
+1
-1
arch/powerpc/kernel/ppc_ksyms.c
+1
-1
arch/powerpc/kernel/ppc_ksyms.c
···
26
26
#include <linux/cuda.h>
27
27
#include <linux/pmu.h>
28
28
#include <asm/prom.h>
29
-
#include <asm/system.h>
30
29
#include <asm/pci-bridge.h>
31
30
#include <asm/irq.h>
32
31
#include <asm/pmac_feature.h>
···
42
43
#include <asm/signal.h>
43
44
#include <asm/dcr.h>
44
45
#include <asm/ftrace.h>
46
+
#include <asm/switch_to.h>
45
47
46
48
#ifdef CONFIG_PPC32
47
49
extern void transfer_to_handler(void);
+3
-1
arch/powerpc/kernel/process.c
+3
-1
arch/powerpc/kernel/process.c
···
41
41
42
42
#include <asm/pgtable.h>
43
43
#include <asm/uaccess.h>
44
-
#include <asm/system.h>
45
44
#include <asm/io.h>
46
45
#include <asm/processor.h>
47
46
#include <asm/mmu.h>
48
47
#include <asm/prom.h>
49
48
#include <asm/machdep.h>
50
49
#include <asm/time.h>
50
+
#include <asm/runlatch.h>
51
51
#include <asm/syscalls.h>
52
+
#include <asm/switch_to.h>
53
+
#include <asm/debug.h>
52
54
#ifdef CONFIG_PPC64
53
55
#include <asm/firmware.h>
54
56
#endif
-1
arch/powerpc/kernel/prom.c
-1
arch/powerpc/kernel/prom.c
-1
arch/powerpc/kernel/prom_init.c
-1
arch/powerpc/kernel/prom_init.c
+1
-1
arch/powerpc/kernel/ptrace.c
+1
-1
arch/powerpc/kernel/ptrace.c
+1
-1
arch/powerpc/kernel/ptrace32.c
+1
-1
arch/powerpc/kernel/ptrace32.c
-1
arch/powerpc/kernel/rtas.c
-1
arch/powerpc/kernel/rtas.c
-1
arch/powerpc/kernel/setup-common.c
-1
arch/powerpc/kernel/setup-common.c
-1
arch/powerpc/kernel/setup_32.c
-1
arch/powerpc/kernel/setup_32.c
-1
arch/powerpc/kernel/setup_64.c
-1
arch/powerpc/kernel/setup_64.c
+1
arch/powerpc/kernel/signal.c
+1
arch/powerpc/kernel/signal.c
+1
arch/powerpc/kernel/signal_32.c
+1
arch/powerpc/kernel/signal_32.c
+1
arch/powerpc/kernel/signal_64.c
+1
arch/powerpc/kernel/signal_64.c
+1
-1
arch/powerpc/kernel/smp.c
+1
-1
arch/powerpc/kernel/smp.c
···
43
43
#include <asm/machdep.h>
44
44
#include <asm/cputhreads.h>
45
45
#include <asm/cputable.h>
46
-
#include <asm/system.h>
47
46
#include <asm/mpic.h>
48
47
#include <asm/vdso_datapage.h>
49
48
#ifdef CONFIG_PPC64
50
49
#include <asm/paca.h>
51
50
#endif
51
+
#include <asm/debug.h>
52
52
53
53
#ifdef DEBUG
54
54
#include <asm/udbg.h>
-1
arch/powerpc/kernel/softemu8xx.c
-1
arch/powerpc/kernel/softemu8xx.c
+1
-1
arch/powerpc/kernel/swsusp.c
+1
-1
arch/powerpc/kernel/swsusp.c
-1
arch/powerpc/kernel/swsusp_64.c
-1
arch/powerpc/kernel/swsusp_64.c
+1
arch/powerpc/kernel/sys_ppc32.c
+1
arch/powerpc/kernel/sys_ppc32.c
-1
arch/powerpc/kernel/sysfs.c
-1
arch/powerpc/kernel/sysfs.c
+2
-1
arch/powerpc/kernel/traps.c
+2
-1
arch/powerpc/kernel/traps.c
···
39
39
#include <asm/emulated_ops.h>
40
40
#include <asm/pgtable.h>
41
41
#include <asm/uaccess.h>
42
-
#include <asm/system.h>
43
42
#include <asm/io.h>
44
43
#include <asm/machdep.h>
45
44
#include <asm/rtas.h>
···
57
58
#include <asm/ppc-opcode.h>
58
59
#include <asm/rio.h>
59
60
#include <asm/fadump.h>
61
+
#include <asm/switch_to.h>
62
+
#include <asm/debug.h>
60
63
61
64
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
62
65
int (*__debugger)(struct pt_regs *regs) __read_mostly;
-1
arch/powerpc/kernel/vdso.c
-1
arch/powerpc/kernel/vdso.c
+1
arch/powerpc/kvm/book3s_hv.c
+1
arch/powerpc/kvm/book3s_hv.c
+1
-1
arch/powerpc/lib/alloc.c
+1
-1
arch/powerpc/lib/alloc.c
+1
arch/powerpc/lib/copyuser_power7_vmx.c
+1
arch/powerpc/lib/copyuser_power7_vmx.c
-1
arch/powerpc/mm/44x_mmu.c
-1
arch/powerpc/mm/44x_mmu.c
+1
-1
arch/powerpc/mm/fault.c
+1
-1
arch/powerpc/mm/fault.c
···
38
38
#include <asm/pgtable.h>
39
39
#include <asm/mmu.h>
40
40
#include <asm/mmu_context.h>
41
-
#include <asm/system.h>
42
41
#include <asm/uaccess.h>
43
42
#include <asm/tlbflush.h>
44
43
#include <asm/siginfo.h>
44
+
#include <asm/debug.h>
45
45
#include <mm/mmu_decl.h>
46
46
47
47
#include "icswx.h"
-1
arch/powerpc/mm/hash_utils_64.c
-1
arch/powerpc/mm/hash_utils_64.c
-1
arch/powerpc/mm/init_32.c
-1
arch/powerpc/mm/init_32.c
-1
arch/powerpc/mm/init_64.c
-1
arch/powerpc/mm/init_64.c
+1
-1
arch/powerpc/mm/numa.c
+1
-1
arch/powerpc/mm/numa.c
···
24
24
#include <linux/node.h>
25
25
#include <asm/sparsemem.h>
26
26
#include <asm/prom.h>
27
-
#include <asm/system.h>
28
27
#include <asm/smp.h>
29
28
#include <asm/firmware.h>
30
29
#include <asm/paca.h>
31
30
#include <asm/hvcall.h>
31
+
#include <asm/setup.h>
32
32
33
33
static int numa_enabled = 1;
34
34
+1
arch/powerpc/mm/pgtable_32.c
+1
arch/powerpc/mm/pgtable_32.c
-1
arch/powerpc/mm/pgtable_64.c
-1
arch/powerpc/mm/pgtable_64.c
-1
arch/powerpc/oprofile/common.c
-1
arch/powerpc/oprofile/common.c
-1
arch/powerpc/oprofile/op_model_7450.c
-1
arch/powerpc/oprofile/op_model_7450.c
-1
arch/powerpc/oprofile/op_model_cell.c
-1
arch/powerpc/oprofile/op_model_cell.c
-1
arch/powerpc/oprofile/op_model_fsl_emb.c
-1
arch/powerpc/oprofile/op_model_fsl_emb.c
-1
arch/powerpc/oprofile/op_model_power4.c
-1
arch/powerpc/oprofile/op_model_power4.c
-1
arch/powerpc/oprofile/op_model_rs64.c
-1
arch/powerpc/oprofile/op_model_rs64.c
+1
arch/powerpc/platforms/52xx/lite5200_pm.c
+1
arch/powerpc/platforms/52xx/lite5200_pm.c
-1
arch/powerpc/platforms/82xx/pq2.c
-1
arch/powerpc/platforms/82xx/pq2.c
-1
arch/powerpc/platforms/83xx/km83xx.c
-1
arch/powerpc/platforms/83xx/km83xx.c
-1
arch/powerpc/platforms/83xx/mpc832x_mds.c
-1
arch/powerpc/platforms/83xx/mpc832x_mds.c
-1
arch/powerpc/platforms/83xx/mpc834x_itx.c
-1
arch/powerpc/platforms/83xx/mpc834x_itx.c
-1
arch/powerpc/platforms/83xx/mpc834x_mds.c
-1
arch/powerpc/platforms/83xx/mpc834x_mds.c
-1
arch/powerpc/platforms/83xx/mpc836x_mds.c
-1
arch/powerpc/platforms/83xx/mpc836x_mds.c
-1
arch/powerpc/platforms/83xx/sbc834x.c
-1
arch/powerpc/platforms/83xx/sbc834x.c
+1
arch/powerpc/platforms/83xx/suspend.c
+1
arch/powerpc/platforms/83xx/suspend.c
-1
arch/powerpc/platforms/85xx/corenet_ds.c
-1
arch/powerpc/platforms/85xx/corenet_ds.c
-1
arch/powerpc/platforms/85xx/ge_imp3a.c
-1
arch/powerpc/platforms/85xx/ge_imp3a.c
-1
arch/powerpc/platforms/85xx/ksi8560.c
-1
arch/powerpc/platforms/85xx/ksi8560.c
-1
arch/powerpc/platforms/85xx/mpc8536_ds.c
-1
arch/powerpc/platforms/85xx/mpc8536_ds.c
-1
arch/powerpc/platforms/85xx/mpc85xx_ads.c
-1
arch/powerpc/platforms/85xx/mpc85xx_ads.c
-1
arch/powerpc/platforms/85xx/mpc85xx_cds.c
-1
arch/powerpc/platforms/85xx/mpc85xx_cds.c
-1
arch/powerpc/platforms/85xx/mpc85xx_ds.c
-1
arch/powerpc/platforms/85xx/mpc85xx_ds.c
-1
arch/powerpc/platforms/85xx/mpc85xx_mds.c
-1
arch/powerpc/platforms/85xx/mpc85xx_mds.c
-1
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
-1
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
-1
arch/powerpc/platforms/85xx/p1010rdb.c
-1
arch/powerpc/platforms/85xx/p1010rdb.c
-1
arch/powerpc/platforms/85xx/p1023_rds.c
-1
arch/powerpc/platforms/85xx/p1023_rds.c
-1
arch/powerpc/platforms/85xx/p2041_rdb.c
-1
arch/powerpc/platforms/85xx/p2041_rdb.c
-1
arch/powerpc/platforms/85xx/p3041_ds.c
-1
arch/powerpc/platforms/85xx/p3041_ds.c
-1
arch/powerpc/platforms/85xx/p4080_ds.c
-1
arch/powerpc/platforms/85xx/p4080_ds.c
-1
arch/powerpc/platforms/85xx/p5020_ds.c
-1
arch/powerpc/platforms/85xx/p5020_ds.c
-1
arch/powerpc/platforms/85xx/sbc8548.c
-1
arch/powerpc/platforms/85xx/sbc8548.c
-1
arch/powerpc/platforms/85xx/sbc8560.c
-1
arch/powerpc/platforms/85xx/sbc8560.c
-1
arch/powerpc/platforms/85xx/socrates.c
-1
arch/powerpc/platforms/85xx/socrates.c
-1
arch/powerpc/platforms/85xx/stx_gp3.c
-1
arch/powerpc/platforms/85xx/stx_gp3.c
-1
arch/powerpc/platforms/85xx/tqm85xx.c
-1
arch/powerpc/platforms/85xx/tqm85xx.c
-1
arch/powerpc/platforms/85xx/xes_mpc85xx.c
-1
arch/powerpc/platforms/85xx/xes_mpc85xx.c
-1
arch/powerpc/platforms/86xx/gef_ppc9a.c
-1
arch/powerpc/platforms/86xx/gef_ppc9a.c
-1
arch/powerpc/platforms/86xx/gef_sbc310.c
-1
arch/powerpc/platforms/86xx/gef_sbc310.c
-1
arch/powerpc/platforms/86xx/gef_sbc610.c
-1
arch/powerpc/platforms/86xx/gef_sbc610.c
-1
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
-1
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
-1
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
-1
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
-1
arch/powerpc/platforms/86xx/pic.c
-1
arch/powerpc/platforms/86xx/pic.c
-1
arch/powerpc/platforms/86xx/sbc8641d.c
-1
arch/powerpc/platforms/86xx/sbc8641d.c
-1
arch/powerpc/platforms/8xx/mpc86xads_setup.c
-1
arch/powerpc/platforms/8xx/mpc86xads_setup.c
-1
arch/powerpc/platforms/8xx/mpc885ads_setup.c
-1
arch/powerpc/platforms/8xx/mpc885ads_setup.c
-1
arch/powerpc/platforms/8xx/tqm8xx_setup.c
-1
arch/powerpc/platforms/8xx/tqm8xx_setup.c
-1
arch/powerpc/platforms/cell/smp.c
-1
arch/powerpc/platforms/cell/smp.c
-1
arch/powerpc/platforms/embedded6xx/c2k.c
-1
arch/powerpc/platforms/embedded6xx/c2k.c
-1
arch/powerpc/platforms/embedded6xx/holly.c
-1
arch/powerpc/platforms/embedded6xx/holly.c
-1
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
-1
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
-1
arch/powerpc/platforms/embedded6xx/prpmc2800.c
-1
arch/powerpc/platforms/embedded6xx/prpmc2800.c
-1
arch/powerpc/platforms/embedded6xx/storcenter.c
-1
arch/powerpc/platforms/embedded6xx/storcenter.c
-1
arch/powerpc/platforms/fsl_uli1575.c
-1
arch/powerpc/platforms/fsl_uli1575.c
-1
arch/powerpc/platforms/maple/setup.c
-1
arch/powerpc/platforms/maple/setup.c
-1
arch/powerpc/platforms/maple/time.c
-1
arch/powerpc/platforms/maple/time.c
+1
-1
arch/powerpc/platforms/pasemi/setup.c
+1
-1
arch/powerpc/platforms/pasemi/setup.c
···
32
32
#include <linux/gfp.h>
33
33
34
34
#include <asm/prom.h>
35
-
#include <asm/system.h>
36
35
#include <asm/iommu.h>
37
36
#include <asm/machdep.h>
38
37
#include <asm/mpic.h>
39
38
#include <asm/smp.h>
40
39
#include <asm/time.h>
41
40
#include <asm/mmu.h>
41
+
#include <asm/debug.h>
42
42
43
43
#include <pcmcia/ss.h>
44
44
#include <pcmcia/cistpl.h>
+1
arch/powerpc/platforms/powermac/bootx_init.c
+1
arch/powerpc/platforms/powermac/bootx_init.c
+1
-1
arch/powerpc/platforms/powermac/cpufreq_32.c
+1
-1
arch/powerpc/platforms/powermac/cpufreq_32.c
···
33
33
#include <asm/sections.h>
34
34
#include <asm/cputable.h>
35
35
#include <asm/time.h>
36
-
#include <asm/system.h>
37
36
#include <asm/mpic.h>
38
37
#include <asm/keylargo.h>
38
+
#include <asm/switch_to.h>
39
39
40
40
/* WARNING !!! This will cause calibrate_delay() to be called,
41
41
* but this is an __init function ! So you MUST go edit
-1
arch/powerpc/platforms/powermac/nvram.c
-1
arch/powerpc/platforms/powermac/nvram.c
-1
arch/powerpc/platforms/powermac/setup.c
-1
arch/powerpc/platforms/powermac/setup.c
-1
arch/powerpc/platforms/powermac/time.c
-1
arch/powerpc/platforms/powermac/time.c
-1
arch/powerpc/platforms/powernv/smp.c
-1
arch/powerpc/platforms/powernv/smp.c
+1
arch/powerpc/platforms/ps3/mm.c
+1
arch/powerpc/platforms/ps3/mm.c
+1
-1
arch/powerpc/platforms/pseries/dtl.c
+1
-1
arch/powerpc/platforms/pseries/dtl.c
-1
arch/powerpc/platforms/pseries/hotplug-cpu.c
-1
arch/powerpc/platforms/pseries/hotplug-cpu.c
+1
-1
arch/powerpc/platforms/pseries/processor_idle.c
+1
-1
arch/powerpc/platforms/pseries/processor_idle.c
-1
arch/powerpc/platforms/pseries/ras.c
-1
arch/powerpc/platforms/pseries/ras.c
-1
arch/powerpc/platforms/pseries/smp.c
-1
arch/powerpc/platforms/pseries/smp.c
-1
arch/powerpc/platforms/wsp/chroma.c
-1
arch/powerpc/platforms/wsp/chroma.c
-1
arch/powerpc/platforms/wsp/psr2.c
-1
arch/powerpc/platforms/wsp/psr2.c
+1
arch/powerpc/platforms/wsp/wsp_pci.c
+1
arch/powerpc/platforms/wsp/wsp_pci.c
-1
arch/powerpc/sysdev/cpm_common.c
-1
arch/powerpc/sysdev/cpm_common.c
-1
arch/powerpc/sysdev/fsl_soc.c
-1
arch/powerpc/sysdev/fsl_soc.c
+1
arch/powerpc/sysdev/msi_bitmap.c
+1
arch/powerpc/sysdev/msi_bitmap.c
-1
arch/powerpc/sysdev/tsi108_dev.c
-1
arch/powerpc/sysdev/tsi108_dev.c
+1
arch/powerpc/xmon/xmon.c
+1
arch/powerpc/xmon/xmon.c