tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Disintegrate asm/system.h for PA-RISC
Disintegrate asm/system.h for PA-RISC.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: linux-parisc@vger.kernel.org
+191
-179
-1
arch/parisc/include/asm/atomic.h
-1
arch/parisc/include/asm/atomic.h
+35
arch/parisc/include/asm/barrier.h
+35
arch/parisc/include/asm/barrier.h
···
1
+
#ifndef __PARISC_BARRIER_H
2
+
#define __PARISC_BARRIER_H
3
+
4
+
/*
5
+
** This is simply the barrier() macro from linux/kernel.h but when serial.c
6
+
** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
7
+
** hasn't yet been included yet so it fails, thus repeating the macro here.
8
+
**
9
+
** PA-RISC architecture allows for weakly ordered memory accesses although
10
+
** none of the processors use it. There is a strong ordered bit that is
11
+
** set in the O-bit of the page directory entry. Operating systems that
12
+
** can not tolerate out of order accesses should set this bit when mapping
13
+
** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
14
+
** of the processor implemented the PSW O-bit). The PCX-W ERS states that
15
+
** the TLB O-bit is not implemented so the page directory does not need to
16
+
** have the O-bit set when mapping pages (section 3.1). This section also
17
+
** states that the PSW Y, Z, G, and O bits are not implemented.
18
+
** So it looks like nothing needs to be done for parisc-linux (yet).
19
+
** (thanks to chada for the above comment -ggg)
20
+
**
21
+
** The __asm__ op below simple prevents gcc/ld from reordering
22
+
** instructions across the mb() "call".
23
+
*/
24
+
#define mb() __asm__ __volatile__("":::"memory") /* barrier() */
25
+
#define rmb() mb()
26
+
#define wmb() mb()
27
+
#define smp_mb() mb()
28
+
#define smp_rmb() mb()
29
+
#define smp_wmb() mb()
30
+
#define smp_read_barrier_depends() do { } while(0)
31
+
#define read_barrier_depends() do { } while(0)
32
+
33
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#define set_mb(var, value) do { var = value; mb(); } while (0)
34
+
35
+
#endif /* __PARISC_BARRIER_H */
+1
-1
arch/parisc/include/asm/delay.h
+1
-1
arch/parisc/include/asm/delay.h
-1
arch/parisc/include/asm/dma.h
-1
arch/parisc/include/asm/dma.h
+6
arch/parisc/include/asm/exec.h
+6
arch/parisc/include/asm/exec.h
+48
arch/parisc/include/asm/ldcw.h
+48
arch/parisc/include/asm/ldcw.h
···
1
+
#ifndef __PARISC_LDCW_H
2
+
#define __PARISC_LDCW_H
3
+
4
+
#ifndef CONFIG_PA20
5
+
/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
6
+
and GCC only guarantees 8-byte alignment for stack locals, we can't
7
+
be assured of 16-byte alignment for atomic lock data even if we
8
+
specify "__attribute ((aligned(16)))" in the type declaration. So,
9
+
we use a struct containing an array of four ints for the atomic lock
10
+
type and dynamically select the 16-byte aligned int from the array
11
+
for the semaphore. */
12
+
13
+
#define __PA_LDCW_ALIGNMENT 16
14
+
#define __ldcw_align(a) ({ \
15
+
unsigned long __ret = (unsigned long) &(a)->lock[0]; \
16
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__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
17
+
& ~(__PA_LDCW_ALIGNMENT - 1); \
18
+
(volatile unsigned int *) __ret; \
19
+
})
20
+
#define __LDCW "ldcw"
21
+
22
+
#else /*CONFIG_PA20*/
23
+
/* From: "Jim Hull" <jim.hull of hp.com>
24
+
I've attached a summary of the change, but basically, for PA 2.0, as
25
+
long as the ",CO" (coherent operation) completer is specified, then the
26
+
16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
27
+
they only require "natural" alignment (4-byte for ldcw, 8-byte for
28
+
ldcd). */
29
+
30
+
#define __PA_LDCW_ALIGNMENT 4
31
+
#define __ldcw_align(a) (&(a)->slock)
32
+
#define __LDCW "ldcw,co"
33
+
34
+
#endif /*!CONFIG_PA20*/
35
+
36
+
/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
37
+
#define __ldcw(a) ({ \
38
+
unsigned __ret; \
39
+
__asm__ __volatile__(__LDCW " 0(%2),%0" \
40
+
: "=r" (__ret), "+m" (*(a)) : "r" (a)); \
41
+
__ret; \
42
+
})
43
+
44
+
#ifdef CONFIG_SMP
45
+
# define __lock_aligned __attribute__((__section__(".data..lock_aligned")))
46
+
#endif
47
+
48
+
#endif /* __PARISC_LDCW_H */
+1
-1
arch/parisc/include/asm/processor.h
+1
-1
arch/parisc/include/asm/processor.h
···
16
16
#include <asm/pdc.h>
17
17
#include <asm/ptrace.h>
18
18
#include <asm/types.h>
19
-
#include <asm/system.h>
20
19
#include <asm/percpu.h>
21
20
22
21
#endif /* __ASSEMBLY__ */
···
168
169
* Return saved PC of a blocked thread. This is used by ps mostly.
169
170
*/
170
171
172
+
struct task_struct;
171
173
unsigned long thread_saved_pc(struct task_struct *t);
172
174
void show_trace(struct task_struct *task, unsigned long *stack);
173
175
+41
arch/parisc/include/asm/psw.h
+41
arch/parisc/include/asm/psw.h
···
59
59
#define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
60
60
#define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
61
61
62
+
#ifndef __ASSEMBLY__
63
+
64
+
/* The program status word as bitfields. */
65
+
struct pa_psw {
66
+
unsigned int y:1;
67
+
unsigned int z:1;
68
+
unsigned int rv:2;
69
+
unsigned int w:1;
70
+
unsigned int e:1;
71
+
unsigned int s:1;
72
+
unsigned int t:1;
73
+
74
+
unsigned int h:1;
75
+
unsigned int l:1;
76
+
unsigned int n:1;
77
+
unsigned int x:1;
78
+
unsigned int b:1;
79
+
unsigned int c:1;
80
+
unsigned int v:1;
81
+
unsigned int m:1;
82
+
83
+
unsigned int cb:8;
84
+
85
+
unsigned int o:1;
86
+
unsigned int g:1;
87
+
unsigned int f:1;
88
+
unsigned int r:1;
89
+
unsigned int q:1;
90
+
unsigned int p:1;
91
+
unsigned int d:1;
92
+
unsigned int i:1;
93
+
};
94
+
95
+
#ifdef CONFIG_64BIT
96
+
#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
97
+
#else
98
+
#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
99
+
#endif
100
+
101
+
#endif /* !__ASSEMBLY__ */
102
+
62
103
#endif
+40
arch/parisc/include/asm/special_insns.h
+40
arch/parisc/include/asm/special_insns.h
···
1
+
#ifndef __PARISC_SPECIAL_INSNS_H
2
+
#define __PARISC_SPECIAL_INSNS_H
3
+
4
+
#define mfctl(reg) ({ \
5
+
unsigned long cr; \
6
+
__asm__ __volatile__( \
7
+
"mfctl " #reg ",%0" : \
8
+
"=r" (cr) \
9
+
); \
10
+
cr; \
11
+
})
12
+
13
+
#define mtctl(gr, cr) \
14
+
__asm__ __volatile__("mtctl %0,%1" \
15
+
: /* no outputs */ \
16
+
: "r" (gr), "i" (cr) : "memory")
17
+
18
+
/* these are here to de-mystefy the calling code, and to provide hooks */
19
+
/* which I needed for debugging EIEM problems -PB */
20
+
#define get_eiem() mfctl(15)
21
+
static inline void set_eiem(unsigned long val)
22
+
{
23
+
mtctl(val, 15);
24
+
}
25
+
26
+
#define mfsp(reg) ({ \
27
+
unsigned long cr; \
28
+
__asm__ __volatile__( \
29
+
"mfsp " #reg ",%0" : \
30
+
"=r" (cr) \
31
+
); \
32
+
cr; \
33
+
})
34
+
35
+
#define mtsp(gr, cr) \
36
+
__asm__ __volatile__("mtsp %0,%1" \
37
+
: /* no outputs */ \
38
+
: "r" (gr), "i" (cr) : "memory")
39
+
40
+
#endif /* __PARISC_SPECIAL_INSNS_H */
-1
arch/parisc/include/asm/spinlock.h
-1
arch/parisc/include/asm/spinlock.h
+12
arch/parisc/include/asm/switch_to.h
+12
arch/parisc/include/asm/switch_to.h
···
1
+
#ifndef __PARISC_SWITCH_TO_H
2
+
#define __PARISC_SWITCH_TO_H
3
+
4
+
struct task_struct;
5
+
6
+
extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
7
+
8
+
#define switch_to(prev, next, last) do { \
9
+
(last) = _switch_to(prev, next); \
10
+
} while(0)
11
+
12
+
#endif /* __PARISC_SWITCH_TO_H */
+6
-165
arch/parisc/include/asm/system.h
+6
-165
arch/parisc/include/asm/system.h
···
1
-
#ifndef __PARISC_SYSTEM_H
2
-
#define __PARISC_SYSTEM_H
3
-
4
-
#include <linux/irqflags.h>
5
-
6
-
/* The program status word as bitfields. */
7
-
struct pa_psw {
8
-
unsigned int y:1;
9
-
unsigned int z:1;
10
-
unsigned int rv:2;
11
-
unsigned int w:1;
12
-
unsigned int e:1;
13
-
unsigned int s:1;
14
-
unsigned int t:1;
15
-
16
-
unsigned int h:1;
17
-
unsigned int l:1;
18
-
unsigned int n:1;
19
-
unsigned int x:1;
20
-
unsigned int b:1;
21
-
unsigned int c:1;
22
-
unsigned int v:1;
23
-
unsigned int m:1;
24
-
25
-
unsigned int cb:8;
26
-
27
-
unsigned int o:1;
28
-
unsigned int g:1;
29
-
unsigned int f:1;
30
-
unsigned int r:1;
31
-
unsigned int q:1;
32
-
unsigned int p:1;
33
-
unsigned int d:1;
34
-
unsigned int i:1;
35
-
};
36
-
37
-
#ifdef CONFIG_64BIT
38
-
#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
39
-
#else
40
-
#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
41
-
#endif
42
-
43
-
struct task_struct;
44
-
45
-
extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
46
-
47
-
#define switch_to(prev, next, last) do { \
48
-
(last) = _switch_to(prev, next); \
49
-
} while(0)
50
-
51
-
#define mfctl(reg) ({ \
52
-
unsigned long cr; \
53
-
__asm__ __volatile__( \
54
-
"mfctl " #reg ",%0" : \
55
-
"=r" (cr) \
56
-
); \
57
-
cr; \
58
-
})
59
-
60
-
#define mtctl(gr, cr) \
61
-
__asm__ __volatile__("mtctl %0,%1" \
62
-
: /* no outputs */ \
63
-
: "r" (gr), "i" (cr) : "memory")
64
-
65
-
/* these are here to de-mystefy the calling code, and to provide hooks */
66
-
/* which I needed for debugging EIEM problems -PB */
67
-
#define get_eiem() mfctl(15)
68
-
static inline void set_eiem(unsigned long val)
69
-
{
70
-
mtctl(val, 15);
71
-
}
72
-
73
-
#define mfsp(reg) ({ \
74
-
unsigned long cr; \
75
-
__asm__ __volatile__( \
76
-
"mfsp " #reg ",%0" : \
77
-
"=r" (cr) \
78
-
); \
79
-
cr; \
80
-
})
81
-
82
-
#define mtsp(gr, cr) \
83
-
__asm__ __volatile__("mtsp %0,%1" \
84
-
: /* no outputs */ \
85
-
: "r" (gr), "i" (cr) : "memory")
86
-
87
-
88
-
/*
89
-
** This is simply the barrier() macro from linux/kernel.h but when serial.c
90
-
** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
91
-
** hasn't yet been included yet so it fails, thus repeating the macro here.
92
-
**
93
-
** PA-RISC architecture allows for weakly ordered memory accesses although
94
-
** none of the processors use it. There is a strong ordered bit that is
95
-
** set in the O-bit of the page directory entry. Operating systems that
96
-
** can not tolerate out of order accesses should set this bit when mapping
97
-
** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
98
-
** of the processor implemented the PSW O-bit). The PCX-W ERS states that
99
-
** the TLB O-bit is not implemented so the page directory does not need to
100
-
** have the O-bit set when mapping pages (section 3.1). This section also
101
-
** states that the PSW Y, Z, G, and O bits are not implemented.
102
-
** So it looks like nothing needs to be done for parisc-linux (yet).
103
-
** (thanks to chada for the above comment -ggg)
104
-
**
105
-
** The __asm__ op below simple prevents gcc/ld from reordering
106
-
** instructions across the mb() "call".
107
-
*/
108
-
#define mb() __asm__ __volatile__("":::"memory") /* barrier() */
109
-
#define rmb() mb()
110
-
#define wmb() mb()
111
-
#define smp_mb() mb()
112
-
#define smp_rmb() mb()
113
-
#define smp_wmb() mb()
114
-
#define smp_read_barrier_depends() do { } while(0)
115
-
#define read_barrier_depends() do { } while(0)
116
-
117
-
#define set_mb(var, value) do { var = value; mb(); } while (0)
118
-
119
-
#ifndef CONFIG_PA20
120
-
/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
121
-
and GCC only guarantees 8-byte alignment for stack locals, we can't
122
-
be assured of 16-byte alignment for atomic lock data even if we
123
-
specify "__attribute ((aligned(16)))" in the type declaration. So,
124
-
we use a struct containing an array of four ints for the atomic lock
125
-
type and dynamically select the 16-byte aligned int from the array
126
-
for the semaphore. */
127
-
128
-
#define __PA_LDCW_ALIGNMENT 16
129
-
#define __ldcw_align(a) ({ \
130
-
unsigned long __ret = (unsigned long) &(a)->lock[0]; \
131
-
__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
132
-
& ~(__PA_LDCW_ALIGNMENT - 1); \
133
-
(volatile unsigned int *) __ret; \
134
-
})
135
-
#define __LDCW "ldcw"
136
-
137
-
#else /*CONFIG_PA20*/
138
-
/* From: "Jim Hull" <jim.hull of hp.com>
139
-
I've attached a summary of the change, but basically, for PA 2.0, as
140
-
long as the ",CO" (coherent operation) completer is specified, then the
141
-
16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
142
-
they only require "natural" alignment (4-byte for ldcw, 8-byte for
143
-
ldcd). */
144
-
145
-
#define __PA_LDCW_ALIGNMENT 4
146
-
#define __ldcw_align(a) (&(a)->slock)
147
-
#define __LDCW "ldcw,co"
148
-
149
-
#endif /*!CONFIG_PA20*/
150
-
151
-
/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
152
-
#define __ldcw(a) ({ \
153
-
unsigned __ret; \
154
-
__asm__ __volatile__(__LDCW " 0(%2),%0" \
155
-
: "=r" (__ret), "+m" (*(a)) : "r" (a)); \
156
-
__ret; \
157
-
})
158
-
159
-
#ifdef CONFIG_SMP
160
-
# define __lock_aligned __attribute__((__section__(".data..lock_aligned")))
161
-
#endif
162
-
163
-
#define arch_align_stack(x) (x)
164
-
165
-
#endif
1
+
/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
2
+
#include <asm/barrier.h>
3
+
#include <asm/exec.h>
4
+
#include <asm/ldcw.h>
5
+
#include <asm/special_insns.h>
6
+
#include <asm/switch_to.h>
+1
arch/parisc/include/asm/thread_info.h
+1
arch/parisc/include/asm/thread_info.h
-1
arch/parisc/include/asm/timex.h
-1
arch/parisc/include/asm/timex.h
-1
arch/parisc/include/asm/uaccess.h
-1
arch/parisc/include/asm/uaccess.h
-1
arch/parisc/kernel/cache.c
-1
arch/parisc/kernel/cache.c
-1
arch/parisc/kernel/firmware.c
-1
arch/parisc/kernel/firmware.c
-1
arch/parisc/kernel/pci.c
-1
arch/parisc/kernel/pci.c
-1
arch/parisc/kernel/ptrace.c
-1
arch/parisc/kernel/ptrace.c
-1
arch/parisc/kernel/smp.c
-1
arch/parisc/kernel/smp.c
-1
arch/parisc/kernel/traps.c
-1
arch/parisc/kernel/traps.c