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Merge branch 'for-v6.18/dt-bindings-clk' into next/clk
+382
+213
Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
+213
Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Axis ARTPEC-8 SoC clock controller
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maintainers:
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- Jesper Nilsson <jesper.nilsson@axis.com>
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description: |
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ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
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units, generating clocks for different domains. Those CMU units are modeled
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as separate device tree nodes, and might depend on each other.
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The root clock in that root tree is an external clock: OSCCLK (25 MHz).
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This external clock must be defined as a fixed-rate clock in dts.
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CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other clocks of function blocks (other CMUs) are usually
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derived from CMU_CMU.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'include/dt-bindings/clock/axis,artpec8-clk.h' header.
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properties:
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compatible:
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enum:
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- axis,artpec8-cmu-cmu
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- axis,artpec8-cmu-bus
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- axis,artpec8-cmu-core
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- axis,artpec8-cmu-cpucl
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- axis,artpec8-cmu-fsys
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- axis,artpec8-cmu-imem
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- axis,artpec8-cmu-peri
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+
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reg:
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maxItems: 1
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+
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clocks:
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minItems: 1
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maxItems: 5
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+
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clock-names:
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minItems: 1
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maxItems: 5
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+
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"#clock-cells":
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const: 1
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+
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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+
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allOf:
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-cmu
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+
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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+
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clock-names:
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items:
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- const: fin_pll
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+
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-bus
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+
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_BUS BUS clock (from CMU_CMU)
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- description: CMU_BUS DLP clock (from CMU_CMU)
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+
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clock-names:
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items:
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- const: fin_pll
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- const: bus
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- const: dlp
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+
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-core
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_CORE main clock (from CMU_CMU)
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- description: CMU_CORE DLP clock (from CMU_CMU)
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+
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clock-names:
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items:
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- const: fin_pll
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- const: main
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- const: dlp
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+
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-cpucl
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+
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_CPUCL switch clock (from CMU_CMU)
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+
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clock-names:
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items:
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- const: fin_pll
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- const: switch
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+
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-fsys
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+
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_FSYS SCAN0 clock (from CMU_CMU)
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- description: CMU_FSYS SCAN1 clock (from CMU_CMU)
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- description: CMU_FSYS BUS clock (from CMU_CMU)
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- description: CMU_FSYS IP clock (from CMU_CMU)
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+
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clock-names:
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items:
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- const: fin_pll
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- const: scan0
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- const: scan1
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- const: bus
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- const: ip
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+
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-imem
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+
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_IMEM ACLK clock (from CMU_CMU)
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- description: CMU_IMEM JPEG clock (from CMU_CMU)
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+
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clock-names:
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items:
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- const: fin_pll
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- const: aclk
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- const: jpeg
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+
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-peri
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+
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_PERI IP clock (from CMU_CMU)
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- description: CMU_PERI AUDIO clock (from CMU_CMU)
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- description: CMU_PERI DISP clock (from CMU_CMU)
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clock-names:
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items:
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- const: fin_pll
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- const: ip
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- const: audio
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- const: disp
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additionalProperties: false
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examples:
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# Clock controller node for CMU_FSYS
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- |
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#include <dt-bindings/clock/axis,artpec8-clk.h>
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cmu_fsys: clock-controller@16c10000 {
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compatible = "axis,artpec8-cmu-fsys";
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reg = <0x16c10000 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;
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clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
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};
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...
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include/dt-bindings/clock/axis,artpec8-clk.h
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include/dt-bindings/clock/axis,artpec8-clk.h
···
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2025 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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* Copyright (c) 2025 Axis Communications AB.
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* https://www.axis.com
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*
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* Device Tree binding constants for ARTPEC-8 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H
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#define _DT_BINDINGS_CLOCK_ARTPEC8_H
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/* CMU_CMU */
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#define CLK_FOUT_SHARED0_PLL 1
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#define CLK_DOUT_SHARED0_DIV2 2
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#define CLK_DOUT_SHARED0_DIV3 3
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#define CLK_DOUT_SHARED0_DIV4 4
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#define CLK_FOUT_SHARED1_PLL 5
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#define CLK_DOUT_SHARED1_DIV2 6
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#define CLK_DOUT_SHARED1_DIV3 7
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#define CLK_DOUT_SHARED1_DIV4 8
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#define CLK_FOUT_AUDIO_PLL 9
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#define CLK_DOUT_CMU_BUS 10
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#define CLK_DOUT_CMU_BUS_DLP 11
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#define CLK_DOUT_CMU_CDC_CORE 12
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#define CLK_DOUT_CMU_OTP 13
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#define CLK_DOUT_CMU_CORE_MAIN 14
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#define CLK_DOUT_CMU_CORE_DLP 15
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#define CLK_DOUT_CMU_CPUCL_SWITCH 16
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#define CLK_DOUT_CMU_DLP_CORE 17
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#define CLK_DOUT_CMU_FSYS_BUS 18
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#define CLK_DOUT_CMU_FSYS_IP 19
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#define CLK_DOUT_CMU_FSYS_SCAN0 20
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#define CLK_DOUT_CMU_FSYS_SCAN1 21
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#define CLK_DOUT_CMU_GPU_3D 22
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#define CLK_DOUT_CMU_GPU_2D 23
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#define CLK_DOUT_CMU_IMEM_ACLK 24
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#define CLK_DOUT_CMU_IMEM_JPEG 25
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#define CLK_DOUT_CMU_MIF_SWITCH 26
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#define CLK_DOUT_CMU_MIF_BUSP 27
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#define CLK_DOUT_CMU_PERI_DISP 28
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#define CLK_DOUT_CMU_PERI_IP 29
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#define CLK_DOUT_CMU_PERI_AUDIO 30
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#define CLK_DOUT_CMU_RSP_CORE 31
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#define CLK_DOUT_CMU_TRFM_CORE 32
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#define CLK_DOUT_CMU_VCA_ACE 33
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#define CLK_DOUT_CMU_VCA_OD 34
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#define CLK_DOUT_CMU_VIO_CORE 35
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#define CLK_DOUT_CMU_VIO_AUDIO 36
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#define CLK_DOUT_CMU_VIP0_CORE 37
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#define CLK_DOUT_CMU_VIP1_CORE 38
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#define CLK_DOUT_CMU_VPP_CORE 39
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/* CMU_BUS */
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#define CLK_MOUT_BUS_ACLK_USER 1
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#define CLK_MOUT_BUS_DLP_USER 2
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#define CLK_DOUT_BUS_PCLK 3
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/* CMU_CORE */
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#define CLK_MOUT_CORE_ACLK_USER 1
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#define CLK_MOUT_CORE_DLP_USER 2
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#define CLK_DOUT_CORE_PCLK 3
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/* CMU_CPUCL */
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#define CLK_FOUT_CPUCL_PLL 1
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#define CLK_MOUT_CPUCL_PLL 2
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#define CLK_MOUT_CPUCL_SWITCH_USER 3
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#define CLK_DOUT_CPUCL_CPU 4
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#define CLK_DOUT_CPUCL_CLUSTER_ACLK 5
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#define CLK_DOUT_CPUCL_CLUSTER_PCLKDBG 6
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#define CLK_DOUT_CPUCL_CLUSTER_CNTCLK 7
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#define CLK_DOUT_CPUCL_CLUSTER_ATCLK 8
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#define CLK_DOUT_CPUCL_PCLK 9
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#define CLK_DOUT_CPUCL_CMUREF 10
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#define CLK_DOUT_CPUCL_DBG 11
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#define CLK_DOUT_CPUCL_PCLKDBG 12
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#define CLK_GOUT_CPUCL_CLUSTER_CPU 13
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#define CLK_GOUT_CPUCL_SHORTSTOP 14
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#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 15
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#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 16
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/* CMU_FSYS */
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#define CLK_FOUT_FSYS_PLL 1
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#define CLK_MOUT_FSYS_SCAN0_USER 2
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#define CLK_MOUT_FSYS_SCAN1_USER 3
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#define CLK_MOUT_FSYS_BUS_USER 4
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#define CLK_MOUT_FSYS_MMC_USER 5
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#define CLK_DOUT_FSYS_PCIE_PIPE 6
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#define CLK_DOUT_FSYS_ADC 7
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#define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL 8
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#define CLK_DOUT_FSYS_EQOS_INT125 9
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#define CLK_DOUT_FSYS_OTP_MEM 10
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#define CLK_DOUT_FSYS_SCLK_UART 11
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#define CLK_DOUT_FSYS_EQOS_25 12
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#define CLK_DOUT_FSYS_EQOS_2p5 13
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#define CLK_DOUT_FSYS_BUS300 14
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#define CLK_DOUT_FSYS_BUS_QSPI 15
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#define CLK_DOUT_FSYS_MMC_CARD0 16
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#define CLK_DOUT_FSYS_MMC_CARD1 17
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#define CLK_DOUT_SCAN_CLK_FSYS_125 18
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#define CLK_DOUT_FSYS_QSPI 19
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#define CLK_DOUT_FSYS_SFMC_NAND 20
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#define CLK_DOUT_FSYS_SCAN_CLK_MMC 21
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#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 22
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#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 23
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#define CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK 24
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#define CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK 25
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#define CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK 26
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#define CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK 27
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#define CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0 28
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#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 29
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#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG 30
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#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 31
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#define CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK 32
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#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I 33
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#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I 34
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#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5 35
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#define CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND 36
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#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN 37
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#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK 38
122
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#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN 39
123
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#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK 40
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#define CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN 41
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#define CLK_GOUT_FSYS_UART0_PCLK 42
126
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#define CLK_GOUT_FSYS_UART0_SCLK_UART 43
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#define CLK_GOUT_FSYS_BUS_QSPI 44
128
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#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK 45
129
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#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK 46
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131
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/* CMU_IMEM */
132
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#define CLK_MOUT_IMEM_ACLK_USER 1
133
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#define CLK_MOUT_IMEM_GIC_CA53 2
134
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#define CLK_MOUT_IMEM_GIC_CA5 3
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#define CLK_MOUT_IMEM_JPEG_USER 4
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#define CLK_GOUT_IMEM_MCT_PCLK 5
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#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 6
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+
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/* CMU_PERI */
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#define CLK_MOUT_PERI_IP_USER 1
141
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#define CLK_MOUT_PERI_AUDIO_USER 2
142
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#define CLK_MOUT_PERI_I2S0 3
143
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#define CLK_MOUT_PERI_I2S1 4
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#define CLK_MOUT_PERI_DISP_USER 5
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#define CLK_DOUT_PERI_SPI 6
146
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#define CLK_DOUT_PERI_UART1 7
147
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#define CLK_DOUT_PERI_UART2 8
148
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#define CLK_DOUT_PERI_PCLK 9
149
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#define CLK_DOUT_PERI_I2S0 10
150
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#define CLK_DOUT_PERI_I2S1 11
151
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#define CLK_DOUT_PERI_DSIM 12
152
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#define CLK_GOUT_PERI_UART1_PCLK 13
153
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#define CLK_GOUT_PERI_UART1_SCLK_UART 14
154
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#define CLK_GOUT_PERI_UART2_PCLK 15
155
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#define CLK_GOUT_PERI_UART2_SCLK_UART 16
156
+
#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 17
157
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#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 18
158
+
#define CLK_GOUT_PERI_SPI0_PCLK 19
159
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#define CLK_GOUT_PERI_SPI0_SCLK_SPI 20
160
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#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 21
161
+
#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST 22
162
+
#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST 23
163
+
#define CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK 24
164
+
#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK 25
165
+
#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK 26
166
+
#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 27
167
+
#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 28
168
+
169
+
#endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */