tjh.dev / kernel
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clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP

Add DPU_BUS and CMUREF mux/div, wire their registers and parents,
and update CLKS_NR_TOP. These use the new IDs appended to the
bindings to avoid ABI changes.

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-5-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

authored by

Denzeel Oliva and committed by
Krzysztof Kozlowski 8c82bb53 76f1e2ee

+27 -1
+27 -1
drivers/clk/samsung/clk-exynos990.c
··· 17 17 #include "clk-pll.h" 18 18 19 19 /* NOTE: Must be equal to the last clock ID increased by one */ 20 - #define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1) 20 + #define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1) 21 21 #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1) 22 22 #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1) 23 23 ··· 45 45 #define PLL_CON3_PLL_SHARED3 0x024c 46 46 #define PLL_CON0_PLL_SHARED4 0x0280 47 47 #define PLL_CON3_PLL_SHARED4 0x028c 48 + #define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000 48 49 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004 49 50 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008 50 51 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c ··· 104 103 #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0 105 104 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4 106 105 #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8 106 + #define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0 107 + #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4 107 108 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800 108 109 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804 109 110 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808 ··· 165 162 #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0 166 163 #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8 167 164 #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec 165 + #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0 168 166 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4 169 167 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8 170 168 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc ··· 257 253 PLL_CON3_PLL_SHARED3, 258 254 PLL_CON0_PLL_SHARED4, 259 255 PLL_CON3_PLL_SHARED4, 256 + CLK_CON_MUX_CLKCMU_DPU_BUS, 260 257 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 261 258 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 262 259 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, ··· 316 311 CLK_CON_MUX_MUX_CLKCMU_SSP_BUS, 317 312 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 318 313 CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 314 + CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 315 + CLK_CON_MUX_MUX_CMU_CMUREF, 319 316 CLK_CON_DIV_CLKCMU_APM_BUS, 320 317 CLK_CON_DIV_CLKCMU_AUD_CPU, 321 318 CLK_CON_DIV_CLKCMU_BUS0_BUS, ··· 377 370 CLK_CON_DIV_CLKCMU_VRA_BUS, 378 371 CLK_CON_DIV_DIV_CLKCMU_DPU, 379 372 CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 373 + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 380 374 CLK_CON_DIV_PLL_SHARED0_DIV2, 381 375 CLK_CON_DIV_PLL_SHARED0_DIV3, 382 376 CLK_CON_DIV_PLL_SHARED0_DIV4, ··· 473 465 PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" }; 474 466 PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" }; 475 467 PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" }; 468 + PNAME(mout_cmu_dpu_bus_p) = { "dout_cmu_dpu", 469 + "dout_cmu_dpu_alt" }; 476 470 PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2", 477 471 "dout_cmu_shared2_div2" }; 478 472 PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2", ··· 689 679 "dout_cmu_shared4_div2", 690 680 "dout_cmu_shared0_div4", 691 681 "dout_cmu_shared4_div3" }; 682 + PNAME(mout_cmu_cmuref_p) = { "oscclk", 683 + "dout_cmu_clk_cmuref" }; 684 + PNAME(mout_cmu_clk_cmuref_p) = { "dout_cmu_shared0_div4", 685 + "dout_cmu_shared1_div4", 686 + "dout_cmu_shared2_div2", 687 + "oscclk" }; 692 688 693 689 /* 694 690 * Register name to clock name mangling strategy used in this file ··· 725 709 PLL_CON0_PLL_MMC, 4, 1), 726 710 MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p, 727 711 PLL_CON0_PLL_G3D, 4, 1), 712 + MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", 713 + mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1), 728 714 MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus", 729 715 mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 730 716 MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu", ··· 855 837 mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), 856 838 MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus", 857 839 mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2), 840 + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", 841 + mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), 842 + MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref", 843 + mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2), 858 844 }; 859 845 860 846 static const struct samsung_div_clock top_div_clks[] __initconst = { ··· 1003 981 CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4), 1004 982 DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu", 1005 983 CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3), 984 + DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus", 985 + CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4), 986 + DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref", 987 + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), 1006 988 }; 1007 989 1008 990 static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {