tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amdgpu: remove unnecessary conversion to bool

Better clean that up before some automation starts to complain about it

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Nirmoy Das and committed by
Alex Deucher a9d4fe2f 4c461d89

+50 -50
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
··· 527 527 enum amd_powergating_state state) 528 528 { 529 529 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 530 - bool enable = state == AMD_PG_STATE_GATE ? true : false; 530 + bool enable = (state == AMD_PG_STATE_GATE); 531 531 532 532 if (adev->powerplay.pp_funcs && 533 533 adev->powerplay.pp_funcs->set_powergating_by_smu)
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 985 985 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) 986 986 { 987 987 struct sysinfo si; 988 - bool is_os_64 = (sizeof(void *) == 8) ? true : false; 988 + bool is_os_64 = (sizeof(void *) == 8); 989 989 uint64_t total_memory; 990 990 uint64_t dram_size_seven_GB = 0x1B8000000; 991 991 uint64_t dram_size_three_GB = 0xB8000000;
+2 -2
drivers/gpu/drm/amd/amdgpu/athub_v1_0.c
··· 74 74 case CHIP_VEGA20: 75 75 case CHIP_RAVEN: 76 76 athub_update_medium_grain_clock_gating(adev, 77 - state == AMD_CG_STATE_GATE ? true : false); 77 + state == AMD_CG_STATE_GATE); 78 78 athub_update_medium_grain_light_sleep(adev, 79 - state == AMD_CG_STATE_GATE ? true : false); 79 + state == AMD_CG_STATE_GATE); 80 80 break; 81 81 default: 82 82 break;
+2 -2
drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
··· 77 77 case CHIP_NAVI14: 78 78 case CHIP_NAVI12: 79 79 athub_v2_0_update_medium_grain_clock_gating(adev, 80 - state == AMD_CG_STATE_GATE ? true : false); 80 + state == AMD_CG_STATE_GATE); 81 81 athub_v2_0_update_medium_grain_light_sleep(adev, 82 - state == AMD_CG_STATE_GATE ? true : false); 82 + state == AMD_CG_STATE_GATE); 83 83 break; 84 84 default: 85 85 break;
+2 -2
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 4229 4229 enum amd_powergating_state state) 4230 4230 { 4231 4231 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4232 - bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 4232 + bool enable = (state == AMD_PG_STATE_GATE); 4233 4233 switch (adev->asic_type) { 4234 4234 case CHIP_NAVI10: 4235 4235 case CHIP_NAVI14: ··· 4255 4255 case CHIP_NAVI14: 4256 4256 case CHIP_NAVI12: 4257 4257 gfx_v10_0_update_gfx_clock_gating(adev, 4258 - state == AMD_CG_STATE_GATE ? true : false); 4258 + state == AMD_CG_STATE_GATE); 4259 4259 break; 4260 4260 default: 4261 4261 break;
+2 -2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 4652 4652 enum amd_powergating_state state) 4653 4653 { 4654 4654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4655 - bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 4655 + bool enable = (state == AMD_PG_STATE_GATE); 4656 4656 4657 4657 switch (adev->asic_type) { 4658 4658 case CHIP_RAVEN: ··· 4714 4714 case CHIP_ARCTURUS: 4715 4715 case CHIP_RENOIR: 4716 4716 gfx_v9_0_update_gfx_clock_gating(adev, 4717 - state == AMD_CG_STATE_GATE ? true : false); 4717 + state == AMD_CG_STATE_GATE); 4718 4718 break; 4719 4719 default: 4720 4720 break;
+1 -1
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
··· 690 690 enum amd_clockgating_state state) 691 691 { 692 692 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 693 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 693 + bool enable = (state == AMD_CG_STATE_GATE); 694 694 695 695 if (enable) { 696 696 if (jpeg_v2_0_is_idle(handle))
+1 -1
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
··· 469 469 enum amd_clockgating_state state) 470 470 { 471 471 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 472 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 472 + bool enable = (state == AMD_CG_STATE_GATE); 473 473 int i; 474 474 475 475 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
+2 -2
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
··· 523 523 case CHIP_RAVEN: 524 524 case CHIP_RENOIR: 525 525 mmhub_v1_0_update_medium_grain_clock_gating(adev, 526 - state == AMD_CG_STATE_GATE ? true : false); 526 + state == AMD_CG_STATE_GATE); 527 527 mmhub_v1_0_update_medium_grain_light_sleep(adev, 528 - state == AMD_CG_STATE_GATE ? true : false); 528 + state == AMD_CG_STATE_GATE); 529 529 break; 530 530 default: 531 531 break;
+2 -2
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
··· 427 427 case CHIP_NAVI14: 428 428 case CHIP_NAVI12: 429 429 mmhub_v2_0_update_medium_grain_clock_gating(adev, 430 - state == AMD_CG_STATE_GATE ? true : false); 430 + state == AMD_CG_STATE_GATE); 431 431 mmhub_v2_0_update_medium_grain_light_sleep(adev, 432 - state == AMD_CG_STATE_GATE ? true : false); 432 + state == AMD_CG_STATE_GATE); 433 433 break; 434 434 default: 435 435 break;
+2 -2
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
··· 625 625 switch (adev->asic_type) { 626 626 case CHIP_ARCTURUS: 627 627 mmhub_v9_4_update_medium_grain_clock_gating(adev, 628 - state == AMD_CG_STATE_GATE ? true : false); 628 + state == AMD_CG_STATE_GATE); 629 629 mmhub_v9_4_update_medium_grain_light_sleep(adev, 630 - state == AMD_CG_STATE_GATE ? true : false); 630 + state == AMD_CG_STATE_GATE); 631 631 break; 632 632 default: 633 633 break;
+1 -1
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
··· 426 426 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 427 427 428 428 navi10_ih_update_clockgating_state(adev, 429 - state == AMD_CG_STATE_GATE ? true : false); 429 + state == AMD_CG_STATE_GATE); 430 430 return 0; 431 431 } 432 432
+4 -4
drivers/gpu/drm/amd/amdgpu/nv.c
··· 950 950 case CHIP_NAVI14: 951 951 case CHIP_NAVI12: 952 952 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 953 - state == AMD_CG_STATE_GATE ? true : false); 953 + state == AMD_CG_STATE_GATE); 954 954 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 955 - state == AMD_CG_STATE_GATE ? true : false); 955 + state == AMD_CG_STATE_GATE); 956 956 nv_update_hdp_mem_power_gating(adev, 957 - state == AMD_CG_STATE_GATE ? true : false); 957 + state == AMD_CG_STATE_GATE); 958 958 nv_update_hdp_clock_gating(adev, 959 - state == AMD_CG_STATE_GATE ? true : false); 959 + state == AMD_CG_STATE_GATE); 960 960 break; 961 961 default: 962 962 break;
+2 -2
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
··· 2176 2176 case CHIP_ARCTURUS: 2177 2177 case CHIP_RENOIR: 2178 2178 sdma_v4_0_update_medium_grain_clock_gating(adev, 2179 - state == AMD_CG_STATE_GATE ? true : false); 2179 + state == AMD_CG_STATE_GATE); 2180 2180 sdma_v4_0_update_medium_grain_light_sleep(adev, 2181 - state == AMD_CG_STATE_GATE ? true : false); 2181 + state == AMD_CG_STATE_GATE); 2182 2182 break; 2183 2183 default: 2184 2184 break;
+2 -2
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
··· 1525 1525 case CHIP_NAVI14: 1526 1526 case CHIP_NAVI12: 1527 1527 sdma_v5_0_update_medium_grain_clock_gating(adev, 1528 - state == AMD_CG_STATE_GATE ? true : false); 1528 + state == AMD_CG_STATE_GATE); 1529 1529 sdma_v5_0_update_medium_grain_light_sleep(adev, 1530 - state == AMD_CG_STATE_GATE ? true : false); 1530 + state == AMD_CG_STATE_GATE); 1531 1531 break; 1532 1532 default: 1533 1533 break;
+1 -1
drivers/gpu/drm/amd/amdgpu/si_dma.c
··· 648 648 bool enable; 649 649 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 650 650 651 - enable = (state == AMD_CG_STATE_GATE) ? true : false; 651 + enable = (state == AMD_CG_STATE_GATE); 652 652 653 653 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 654 654 for (i = 0; i < adev->sdma.num_instances; i++) {
+14 -14
drivers/gpu/drm/amd/amdgpu/soc15.c
··· 1467 1467 case CHIP_VEGA12: 1468 1468 case CHIP_VEGA20: 1469 1469 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1470 - state == AMD_CG_STATE_GATE ? true : false); 1470 + state == AMD_CG_STATE_GATE); 1471 1471 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1472 - state == AMD_CG_STATE_GATE ? true : false); 1472 + state == AMD_CG_STATE_GATE); 1473 1473 soc15_update_hdp_light_sleep(adev, 1474 - state == AMD_CG_STATE_GATE ? true : false); 1474 + state == AMD_CG_STATE_GATE); 1475 1475 soc15_update_drm_clock_gating(adev, 1476 - state == AMD_CG_STATE_GATE ? true : false); 1476 + state == AMD_CG_STATE_GATE); 1477 1477 soc15_update_drm_light_sleep(adev, 1478 - state == AMD_CG_STATE_GATE ? true : false); 1478 + state == AMD_CG_STATE_GATE); 1479 1479 soc15_update_rom_medium_grain_clock_gating(adev, 1480 - state == AMD_CG_STATE_GATE ? true : false); 1480 + state == AMD_CG_STATE_GATE); 1481 1481 adev->df.funcs->update_medium_grain_clock_gating(adev, 1482 - state == AMD_CG_STATE_GATE ? true : false); 1482 + state == AMD_CG_STATE_GATE); 1483 1483 break; 1484 1484 case CHIP_RAVEN: 1485 1485 case CHIP_RENOIR: 1486 1486 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1487 - state == AMD_CG_STATE_GATE ? true : false); 1487 + state == AMD_CG_STATE_GATE); 1488 1488 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1489 - state == AMD_CG_STATE_GATE ? true : false); 1489 + state == AMD_CG_STATE_GATE); 1490 1490 soc15_update_hdp_light_sleep(adev, 1491 - state == AMD_CG_STATE_GATE ? true : false); 1491 + state == AMD_CG_STATE_GATE); 1492 1492 soc15_update_drm_clock_gating(adev, 1493 - state == AMD_CG_STATE_GATE ? true : false); 1493 + state == AMD_CG_STATE_GATE); 1494 1494 soc15_update_drm_light_sleep(adev, 1495 - state == AMD_CG_STATE_GATE ? true : false); 1495 + state == AMD_CG_STATE_GATE); 1496 1496 soc15_update_rom_medium_grain_clock_gating(adev, 1497 - state == AMD_CG_STATE_GATE ? true : false); 1497 + state == AMD_CG_STATE_GATE); 1498 1498 break; 1499 1499 case CHIP_ARCTURUS: 1500 1500 soc15_update_hdp_light_sleep(adev, 1501 - state == AMD_CG_STATE_GATE ? true : false); 1501 + state == AMD_CG_STATE_GATE); 1502 1502 break; 1503 1503 default: 1504 1504 break;
+1 -1
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
··· 763 763 enum amd_clockgating_state state) 764 764 { 765 765 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 766 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 766 + bool enable = (state == AMD_CG_STATE_GATE); 767 767 768 768 if (enable) { 769 769 /* wait for STATUS to clear */
+1 -1
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
··· 1421 1421 enum amd_clockgating_state state) 1422 1422 { 1423 1423 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1424 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1424 + bool enable = (state == AMD_CG_STATE_GATE); 1425 1425 1426 1426 if (enable) { 1427 1427 /* wait for STATUS to clear */
+1 -1
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
··· 739 739 enum amd_clockgating_state state) 740 740 { 741 741 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 742 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 742 + bool enable = (state == AMD_CG_STATE_GATE); 743 743 int i; 744 744 745 745 if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
+1 -1
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
··· 887 887 enum amd_clockgating_state state) 888 888 { 889 889 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 890 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 890 + bool enable = (state == AMD_CG_STATE_GATE); 891 891 int i; 892 892 893 893 if ((adev->asic_type == CHIP_POLARIS10) ||
+1 -1
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
··· 1346 1346 enum amd_clockgating_state state) 1347 1347 { 1348 1348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1349 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1349 + bool enable = (state == AMD_CG_STATE_GATE); 1350 1350 1351 1351 if (enable) { 1352 1352 /* wait for STATUS to clear */
+1 -1
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
··· 1213 1213 enum amd_clockgating_state state) 1214 1214 { 1215 1215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1216 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1216 + bool enable = (state == AMD_CG_STATE_GATE); 1217 1217 1218 1218 if (enable) { 1219 1219 /* wait for STATUS to clear */
+1 -1
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
··· 1663 1663 enum amd_clockgating_state state) 1664 1664 { 1665 1665 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1666 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1666 + bool enable = (state == AMD_CG_STATE_GATE); 1667 1667 1668 1668 if (amdgpu_sriov_vf(adev)) 1669 1669 return 0;
+1 -1
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
··· 717 717 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 718 718 719 719 vega10_ih_update_clockgating_state(adev, 720 - state == AMD_CG_STATE_GATE ? true : false); 720 + state == AMD_CG_STATE_GATE); 721 721 return 0; 722 722 723 723 }