tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: add RAS support for the gfx block of Arcturus
Implement functions to do the RAS error injection and
query EDC counter.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Dennis Li
and committed by
Alex Deucher
4c461d89
19cf0dd4
+1039
-1
+1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
drivers/gpu/drm/amd/amdgpu/Makefile
+25
-1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+25
-1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
···
48
48
49
49
#include "amdgpu_ras.h"
50
50
51
+
#include "gfx_v9_4.h"
52
+
51
53
#define GFX9_NUM_GFX_RINGS 1
52
54
#define GFX9_MEC_HPD_SIZE 4096
53
55
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
···
1952
1950
.query_ras_error_count = &gfx_v9_0_query_ras_error_count
1953
1951
};
1954
1952
1953
+
static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = {
1954
+
.get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1955
+
.select_se_sh = &gfx_v9_0_select_se_sh,
1956
+
.read_wave_data = &gfx_v9_0_read_wave_data,
1957
+
.read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1958
+
.read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1959
+
.select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
1960
+
.ras_error_inject = &gfx_v9_4_ras_error_inject,
1961
+
.query_ras_error_count = &gfx_v9_4_query_ras_error_count
1962
+
};
1963
+
1955
1964
static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1956
1965
{
1957
1966
u32 gb_addr_config;
···
2014
2001
gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
2015
2002
break;
2016
2003
case CHIP_ARCTURUS:
2004
+
adev->gfx.funcs = &gfx_v9_4_gfx_funcs;
2017
2005
adev->gfx.config.max_hw_contexts = 8;
2018
2006
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2019
2007
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
···
4279
4265
goto fail;
4280
4266
}
4281
4267
4282
-
gfx_v9_0_clear_ras_edc_counter(adev);
4268
+
switch (adev->asic_type)
4269
+
{
4270
+
case CHIP_VEGA20:
4271
+
gfx_v9_0_clear_ras_edc_counter(adev);
4272
+
break;
4273
+
case CHIP_ARCTURUS:
4274
+
gfx_v9_4_clear_ras_edc_counter(adev);
4275
+
break;
4276
+
default:
4277
+
break;
4278
+
}
4283
4279
4284
4280
fail:
4285
4281
amdgpu_ib_free(adev, &ib, NULL);
+978
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
+978
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
···
1
+
/*
2
+
* Copyright 2020 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#include <linux/kernel.h>
25
+
26
+
#include "amdgpu.h"
27
+
#include "amdgpu_gfx.h"
28
+
#include "soc15.h"
29
+
#include "soc15d.h"
30
+
#include "amdgpu_atomfirmware.h"
31
+
#include "amdgpu_pm.h"
32
+
33
+
#include "gc/gc_9_4_1_offset.h"
34
+
#include "gc/gc_9_4_1_sh_mask.h"
35
+
#include "soc15_common.h"
36
+
37
+
#include "gfx_v9_4.h"
38
+
#include "amdgpu_ras.h"
39
+
40
+
static const struct soc15_reg_entry gfx_v9_4_edc_counter_regs[] = {
41
+
/* CPC */
42
+
{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
43
+
{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 },
44
+
/* DC */
45
+
{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
46
+
{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 },
47
+
{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 },
48
+
/* CPF */
49
+
{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
50
+
{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 },
51
+
/* GDS */
52
+
{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
53
+
{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1 },
54
+
{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1 },
55
+
{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1 },
56
+
{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1 },
57
+
/* SPI */
58
+
{ SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1 },
59
+
/* SQ */
60
+
{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16 },
61
+
{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16 },
62
+
{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16 },
63
+
{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16 },
64
+
/* SQC */
65
+
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6 },
66
+
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6 },
67
+
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6 },
68
+
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 0, 4, 6 },
69
+
/* TA */
70
+
{ SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16 },
71
+
/* TCA */
72
+
{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2 },
73
+
/* TCC */
74
+
{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16 },
75
+
{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16 },
76
+
/* TCI */
77
+
{ SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72 },
78
+
/* TCP */
79
+
{ SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16 },
80
+
{ SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16 },
81
+
{ SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16 },
82
+
/* TD */
83
+
{ SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16 },
84
+
/* GCEA */
85
+
{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32 },
86
+
{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32 },
87
+
{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 1, 32 },
88
+
/* RLC */
89
+
{ SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT), 0, 1, 1 },
90
+
{ SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2), 0, 1, 1 },
91
+
};
92
+
93
+
static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num,
94
+
u32 sh_num, u32 instance)
95
+
{
96
+
u32 data;
97
+
98
+
if (instance == 0xffffffff)
99
+
data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
100
+
INSTANCE_BROADCAST_WRITES, 1);
101
+
else
102
+
data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
103
+
instance);
104
+
105
+
if (se_num == 0xffffffff)
106
+
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
107
+
1);
108
+
else
109
+
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
110
+
111
+
if (sh_num == 0xffffffff)
112
+
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,
113
+
1);
114
+
else
115
+
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
116
+
117
+
WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data);
118
+
}
119
+
120
+
static const struct soc15_ras_field_entry gfx_v9_4_ras_fields[] = {
121
+
/* CPC */
122
+
{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
123
+
SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
124
+
SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
125
+
{ "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
126
+
SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
127
+
SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) },
128
+
{ "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
129
+
SOC15_REG_FIELD(DC_EDC_STATE_CNT, SEC_COUNT_ME1),
130
+
SOC15_REG_FIELD(DC_EDC_STATE_CNT, DED_COUNT_ME1) },
131
+
{ "CPC_DC_CSINVOC_RAM_ME1",
132
+
SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
133
+
SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT_ME1),
134
+
SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT_ME1) },
135
+
{ "CPC_DC_RESTORE_RAM_ME1",
136
+
SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
137
+
SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT_ME1),
138
+
SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT_ME1) },
139
+
{ "CPC_DC_CSINVOC_RAM1_ME1",
140
+
SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
141
+
SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT1_ME1),
142
+
SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT1_ME1) },
143
+
{ "CPC_DC_RESTORE_RAM1_ME1",
144
+
SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
145
+
SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT1_ME1),
146
+
SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT1_ME1) },
147
+
148
+
/* CPF */
149
+
{ "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
150
+
SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME2),
151
+
SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME2) },
152
+
{ "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
153
+
SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME1),
154
+
SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME1) },
155
+
{ "CPF_TCIU_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
156
+
SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
157
+
SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) },
158
+
159
+
/* GDS */
160
+
{ "GDS_GRBM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT),
161
+
SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, SEC),
162
+
SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, DED) },
163
+
{ "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
164
+
SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
165
+
SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) },
166
+
{ "GDS_PHY_CMD_RAM_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
167
+
SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
168
+
SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
169
+
{ "GDS_PHY_DATA_RAM_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
170
+
SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SEC),
171
+
SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_DED) },
172
+
{ "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
173
+
SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
174
+
SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
175
+
{ "GDS_ME1_PIPE0_PIPE_MEM",
176
+
SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
177
+
SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
178
+
SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
179
+
{ "GDS_ME1_PIPE1_PIPE_MEM",
180
+
SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
181
+
SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
182
+
SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
183
+
{ "GDS_ME1_PIPE2_PIPE_MEM",
184
+
SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
185
+
SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
186
+
SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
187
+
{ "GDS_ME1_PIPE3_PIPE_MEM",
188
+
SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
189
+
SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
190
+
SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
191
+
192
+
/* SPI */
193
+
{ "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
194
+
SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SEC_COUNT),
195
+
SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_DED_COUNT) },
196
+
{ "SPI_GDS_EXPREQ", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
197
+
SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_SEC_COUNT),
198
+
SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_DED_COUNT) },
199
+
{ "SPI_WB_GRANT_30", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
200
+
SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_SEC_COUNT),
201
+
SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_DED_COUNT) },
202
+
{ "SPI_WB_GRANT_61", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
203
+
SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_61_SEC_COUNT),
204
+
SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_61_DED_COUNT) },
205
+
{ "SPI_LIFE_CNT", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
206
+
SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_SEC_COUNT),
207
+
SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_DED_COUNT) },
208
+
209
+
/* SQ */
210
+
{ "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
211
+
SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
212
+
SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) },
213
+
{ "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
214
+
SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
215
+
SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) },
216
+
{ "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
217
+
SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
218
+
SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) },
219
+
{ "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
220
+
SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
221
+
SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) },
222
+
{ "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
223
+
SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
224
+
SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) },
225
+
{ "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
226
+
SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
227
+
SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) },
228
+
{ "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
229
+
SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
230
+
SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) },
231
+
232
+
/* SQC */
233
+
{ "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
234
+
SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
235
+
SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
236
+
{ "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
237
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
238
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
239
+
{ "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
240
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
241
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
242
+
{ "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
243
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
244
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
245
+
{ "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
246
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
247
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
248
+
{ "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
249
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
250
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
251
+
{ "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
252
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
253
+
SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
254
+
{ "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
255
+
SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
256
+
SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
257
+
{ "SQC_INST_BANKA_UTCL1_MISS_FIFO",
258
+
SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
259
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
260
+
INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT),
261
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
262
+
INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT) },
263
+
{ "SQC_INST_BANKA_MISS_FIFO",
264
+
SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
265
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_SEC_COUNT),
266
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
267
+
INST_BANKA_MISS_FIFO_DED_COUNT) },
268
+
{ "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
269
+
SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
270
+
SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
271
+
{ "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
272
+
SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
273
+
SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
274
+
{ "SQC_DATA_BANKA_HIT_FIFO",
275
+
SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
276
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_SEC_COUNT),
277
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_DED_COUNT) },
278
+
{ "SQC_DATA_BANKA_MISS_FIFO",
279
+
SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
280
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_SEC_COUNT),
281
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
282
+
DATA_BANKA_MISS_FIFO_DED_COUNT) },
283
+
{ "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
284
+
SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
285
+
SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
286
+
{ "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
287
+
SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
288
+
SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
289
+
{ "SQC_INST_BANKB_UTCL1_MISS_FIFO",
290
+
SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
291
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
292
+
INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT),
293
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
294
+
INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT) },
295
+
{ "SQC_INST_BANKB_MISS_FIFO",
296
+
SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
297
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_SEC_COUNT),
298
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
299
+
INST_BANKB_MISS_FIFO_DED_COUNT) },
300
+
{ "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
301
+
SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
302
+
SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
303
+
{ "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
304
+
SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
305
+
SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
306
+
{ "SQC_DATA_BANKB_HIT_FIFO",
307
+
SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
308
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_SEC_COUNT),
309
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_DED_COUNT) },
310
+
{ "SQC_DATA_BANKB_MISS_FIFO",
311
+
SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
312
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_SEC_COUNT),
313
+
SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
314
+
DATA_BANKB_MISS_FIFO_DED_COUNT) },
315
+
{ "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
316
+
SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
317
+
SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
318
+
319
+
/* TA */
320
+
{ "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
321
+
SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
322
+
SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
323
+
{ "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
324
+
SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SEC_COUNT),
325
+
SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_DED_COUNT) },
326
+
{ "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
327
+
SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SEC_COUNT),
328
+
SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_DED_COUNT) },
329
+
{ "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
330
+
SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SEC_COUNT),
331
+
SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_DED_COUNT) },
332
+
{ "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
333
+
SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SEC_COUNT),
334
+
SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_DED_COUNT) },
335
+
336
+
/* TCA */
337
+
{ "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
338
+
SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SEC_COUNT),
339
+
SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_DED_COUNT) },
340
+
{ "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
341
+
SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SEC_COUNT),
342
+
SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_DED_COUNT) },
343
+
344
+
/* TCC */
345
+
{ "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
346
+
SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
347
+
SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
348
+
{ "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
349
+
SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
350
+
SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
351
+
{ "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
352
+
SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
353
+
SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
354
+
{ "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
355
+
SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
356
+
SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
357
+
{ "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
358
+
SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_SEC_COUNT),
359
+
SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_DED_COUNT) },
360
+
{ "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
361
+
SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_SEC_COUNT),
362
+
SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_DED_COUNT) },
363
+
{ "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
364
+
SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_SEC_COUNT),
365
+
SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_DED_COUNT) },
366
+
{ "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
367
+
SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_SEC_COUNT),
368
+
SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_DED_COUNT) },
369
+
{ "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
370
+
SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_SEC_COUNT),
371
+
SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_DED_COUNT) },
372
+
{ "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
373
+
SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SEC_COUNT),
374
+
SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_DED_COUNT) },
375
+
{ "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
376
+
SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SEC_COUNT),
377
+
SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_DED_COUNT) },
378
+
{ "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
379
+
SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
380
+
SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
381
+
{ "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
382
+
SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SEC_COUNT),
383
+
SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_DED_COUNT) },
384
+
{ "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
385
+
SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SEC_COUNT),
386
+
SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_DED_COUNT) },
387
+
{ "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
388
+
SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_SEC_COUNT),
389
+
SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_DED_COUNT) },
390
+
391
+
/* TCI */
392
+
{ "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
393
+
SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SEC_COUNT),
394
+
SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_DED_COUNT) },
395
+
396
+
/* TCP */
397
+
{ "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
398
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
399
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
400
+
{ "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
401
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
402
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
403
+
{ "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
404
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SEC_COUNT),
405
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_DED_COUNT) },
406
+
{ "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
407
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
408
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_DED_COUNT) },
409
+
{ "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
410
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0, 0 },
411
+
{ "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
412
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
413
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
414
+
{ "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
415
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
416
+
SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
417
+
418
+
/* TD */
419
+
{ "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
420
+
SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
421
+
SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
422
+
{ "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
423
+
SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
424
+
SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
425
+
{ "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
426
+
SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SEC_COUNT),
427
+
SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_DED_COUNT) },
428
+
429
+
/* EA */
430
+
{ "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
431
+
SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
432
+
SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
433
+
{ "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
434
+
SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
435
+
SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
436
+
{ "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
437
+
SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
438
+
SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
439
+
{ "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
440
+
SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
441
+
SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
442
+
{ "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
443
+
SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
444
+
SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
445
+
{ "EA_GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
446
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
447
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
448
+
{ "EA_GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
449
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
450
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
451
+
{ "EA_GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
452
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
453
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
454
+
{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
455
+
SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0, 0 },
456
+
{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
457
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT) },
458
+
{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
459
+
SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0, 0 },
460
+
{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
461
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT) },
462
+
{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
463
+
SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0, 0 },
464
+
{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
465
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, IORD_CMDMEM_DED_COUNT) },
466
+
{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
467
+
SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0, 0 },
468
+
{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
469
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_CMDMEM_DED_COUNT) },
470
+
{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
471
+
SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0, 0 },
472
+
{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
473
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_DATAMEM_DED_COUNT) },
474
+
{ "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
475
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0, 0 },
476
+
{ "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
477
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT) },
478
+
{ "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
479
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0, 0 },
480
+
{ "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
481
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT) },
482
+
{ "EA_MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
483
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
484
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_DED_COUNT) },
485
+
{ "EA_MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
486
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
487
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_DED_COUNT) },
488
+
{ "EA_MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
489
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
490
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_DED_COUNT) },
491
+
{ "EA_MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
492
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
493
+
SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_DED_COUNT) },
494
+
{ "EA_MAM_A0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
495
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_SEC_COUNT),
496
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_DED_COUNT) },
497
+
{ "EA_MAM_A1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
498
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_SEC_COUNT),
499
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_DED_COUNT) },
500
+
{ "EA_MAM_A2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
501
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_SEC_COUNT),
502
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_DED_COUNT) },
503
+
{ "EA_MAM_A3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
504
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_SEC_COUNT),
505
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_DED_COUNT) },
506
+
{ "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
507
+
SOC15_REG_FIELD(GCEA_EDC_CNT, MAM_AFMEM_SEC_COUNT), 0, 0 },
508
+
{ "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
509
+
SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_DED_COUNT) },
510
+
511
+
/* RLC */
512
+
{ "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
513
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_SEC_COUNT),
514
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_DED_COUNT) },
515
+
{ "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
516
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_SEC_COUNT),
517
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_DED_COUNT) },
518
+
{ "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
519
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_SEC_COUNT),
520
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_DED_COUNT) },
521
+
{ "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
522
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_SEC_COUNT),
523
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_DED_COUNT) },
524
+
{ "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
525
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_SEC_COUNT),
526
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_DED_COUNT) },
527
+
{ "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
528
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_SEC_COUNT),
529
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_DED_COUNT) },
530
+
{ "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
531
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_SEC_COUNT),
532
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_DED_COUNT) },
533
+
{ "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
534
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_SEC_COUNT),
535
+
SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_DED_COUNT) },
536
+
{ "RLC_SPM_SE0_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
537
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT),
538
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT) },
539
+
{ "RLC_SPM_SE1_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
540
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT),
541
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT) },
542
+
{ "RLC_SPM_SE2_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
543
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT),
544
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT) },
545
+
{ "RLC_SPM_SE3_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
546
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT),
547
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT) },
548
+
{ "RLC_SPM_SE4_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
549
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT),
550
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT) },
551
+
{ "RLC_SPM_SE5_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
552
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT),
553
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT) },
554
+
{ "RLC_SPM_SE6_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
555
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT),
556
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT) },
557
+
{ "RLC_SPM_SE7_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
558
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT),
559
+
SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT) },
560
+
};
561
+
562
+
static const char * const vml2_mems[] = {
563
+
"UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
564
+
"UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
565
+
"UTC_VML2_BANK_CACHE_0_4K_MEM0",
566
+
"UTC_VML2_BANK_CACHE_0_4K_MEM1",
567
+
"UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
568
+
"UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
569
+
"UTC_VML2_BANK_CACHE_1_4K_MEM0",
570
+
"UTC_VML2_BANK_CACHE_1_4K_MEM1",
571
+
"UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
572
+
"UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
573
+
"UTC_VML2_BANK_CACHE_2_4K_MEM0",
574
+
"UTC_VML2_BANK_CACHE_2_4K_MEM1",
575
+
"UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
576
+
"UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
577
+
"UTC_VML2_BANK_CACHE_3_4K_MEM0",
578
+
"UTC_VML2_BANK_CACHE_3_4K_MEM1",
579
+
"UTC_VML2_IFIFO_GROUP0",
580
+
"UTC_VML2_IFIFO_GROUP1",
581
+
"UTC_VML2_IFIFO_GROUP2",
582
+
"UTC_VML2_IFIFO_GROUP3",
583
+
"UTC_VML2_IFIFO_GROUP4",
584
+
"UTC_VML2_IFIFO_GROUP5",
585
+
"UTC_VML2_IFIFO_GROUP6",
586
+
"UTC_VML2_IFIFO_GROUP7",
587
+
"UTC_VML2_IFIFO_GROUP8",
588
+
"UTC_VML2_IFIFO_GROUP9",
589
+
"UTC_VML2_IFIFO_GROUP10",
590
+
"UTC_VML2_IFIFO_GROUP11",
591
+
"UTC_VML2_IFIFO_GROUP12",
592
+
"UTC_VML2_IFIFO_GROUP13",
593
+
"UTC_VML2_IFIFO_GROUP14",
594
+
"UTC_VML2_IFIFO_GROUP15",
595
+
"UTC_VML2_IFIFO_GROUP16",
596
+
"UTC_VML2_IFIFO_GROUP17",
597
+
"UTC_VML2_IFIFO_GROUP18",
598
+
"UTC_VML2_IFIFO_GROUP19",
599
+
"UTC_VML2_IFIFO_GROUP20",
600
+
"UTC_VML2_IFIFO_GROUP21",
601
+
"UTC_VML2_IFIFO_GROUP22",
602
+
"UTC_VML2_IFIFO_GROUP23",
603
+
"UTC_VML2_IFIFO_GROUP24",
604
+
};
605
+
606
+
static const char * const vml2_walker_mems[] = {
607
+
"UTC_VML2_CACHE_PDE0_MEM0",
608
+
"UTC_VML2_CACHE_PDE0_MEM1",
609
+
"UTC_VML2_CACHE_PDE1_MEM0",
610
+
"UTC_VML2_CACHE_PDE1_MEM1",
611
+
"UTC_VML2_CACHE_PDE2_MEM0",
612
+
"UTC_VML2_CACHE_PDE2_MEM1",
613
+
"UTC_VML2_RDIF_ARADDRS",
614
+
"UTC_VML2_RDIF_LOG_FIFO",
615
+
"UTC_VML2_QUEUE_REQ",
616
+
"UTC_VML2_QUEUE_RET",
617
+
};
618
+
619
+
static const char * const utcl2_router_mems[] = {
620
+
"UTCL2_ROUTER_GROUP0_VML2_REQ_FIFO0",
621
+
"UTCL2_ROUTER_GROUP1_VML2_REQ_FIFO1",
622
+
"UTCL2_ROUTER_GROUP2_VML2_REQ_FIFO2",
623
+
"UTCL2_ROUTER_GROUP3_VML2_REQ_FIFO3",
624
+
"UTCL2_ROUTER_GROUP4_VML2_REQ_FIFO4",
625
+
"UTCL2_ROUTER_GROUP5_VML2_REQ_FIFO5",
626
+
"UTCL2_ROUTER_GROUP6_VML2_REQ_FIFO6",
627
+
"UTCL2_ROUTER_GROUP7_VML2_REQ_FIFO7",
628
+
"UTCL2_ROUTER_GROUP8_VML2_REQ_FIFO8",
629
+
"UTCL2_ROUTER_GROUP9_VML2_REQ_FIFO9",
630
+
"UTCL2_ROUTER_GROUP10_VML2_REQ_FIFO10",
631
+
"UTCL2_ROUTER_GROUP11_VML2_REQ_FIFO11",
632
+
"UTCL2_ROUTER_GROUP12_VML2_REQ_FIFO12",
633
+
"UTCL2_ROUTER_GROUP13_VML2_REQ_FIFO13",
634
+
"UTCL2_ROUTER_GROUP14_VML2_REQ_FIFO14",
635
+
"UTCL2_ROUTER_GROUP15_VML2_REQ_FIFO15",
636
+
"UTCL2_ROUTER_GROUP16_VML2_REQ_FIFO16",
637
+
"UTCL2_ROUTER_GROUP17_VML2_REQ_FIFO17",
638
+
"UTCL2_ROUTER_GROUP18_VML2_REQ_FIFO18",
639
+
"UTCL2_ROUTER_GROUP19_VML2_REQ_FIFO19",
640
+
"UTCL2_ROUTER_GROUP20_VML2_REQ_FIFO20",
641
+
"UTCL2_ROUTER_GROUP21_VML2_REQ_FIFO21",
642
+
"UTCL2_ROUTER_GROUP22_VML2_REQ_FIFO22",
643
+
"UTCL2_ROUTER_GROUP23_VML2_REQ_FIFO23",
644
+
"UTCL2_ROUTER_GROUP24_VML2_REQ_FIFO24",
645
+
};
646
+
647
+
static const char * const atc_l2_cache_2m_mems[] = {
648
+
"UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
649
+
"UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
650
+
"UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
651
+
"UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
652
+
};
653
+
654
+
static const char * const atc_l2_cache_4k_mems[] = {
655
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
656
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
657
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
658
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
659
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
660
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
661
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
662
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
663
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
664
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
665
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
666
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
667
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
668
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
669
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
670
+
"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
671
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
672
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
673
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
674
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
675
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
676
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
677
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
678
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
679
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
680
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
681
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
682
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
683
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
684
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
685
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
686
+
"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
687
+
};
688
+
689
+
static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev,
690
+
struct ras_err_data *err_data)
691
+
{
692
+
uint32_t i, data;
693
+
uint32_t sec_count, ded_count;
694
+
695
+
WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
696
+
WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0);
697
+
WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
698
+
WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0);
699
+
WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
700
+
WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0);
701
+
702
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
703
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
704
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
705
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
706
+
707
+
for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
708
+
WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, i);
709
+
data = RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);
710
+
711
+
sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT);
712
+
if (sec_count) {
713
+
DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
714
+
vml2_mems[i], sec_count);
715
+
err_data->ce_count += sec_count;
716
+
}
717
+
718
+
ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT);
719
+
if (ded_count) {
720
+
DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
721
+
vml2_mems[i], ded_count);
722
+
err_data->ue_count += ded_count;
723
+
}
724
+
}
725
+
726
+
for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
727
+
WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, i);
728
+
data = RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);
729
+
730
+
sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
731
+
SEC_COUNT);
732
+
if (sec_count) {
733
+
DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
734
+
vml2_walker_mems[i], sec_count);
735
+
err_data->ce_count += sec_count;
736
+
}
737
+
738
+
ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
739
+
DED_COUNT);
740
+
if (ded_count) {
741
+
DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
742
+
vml2_walker_mems[i], ded_count);
743
+
err_data->ue_count += ded_count;
744
+
}
745
+
}
746
+
747
+
for (i = 0; i < ARRAY_SIZE(utcl2_router_mems); i++) {
748
+
WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, i);
749
+
data = RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);
750
+
751
+
sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT);
752
+
if (sec_count) {
753
+
DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
754
+
utcl2_router_mems[i], sec_count);
755
+
err_data->ce_count += sec_count;
756
+
}
757
+
758
+
ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT);
759
+
if (ded_count) {
760
+
DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
761
+
utcl2_router_mems[i], ded_count);
762
+
err_data->ue_count += ded_count;
763
+
}
764
+
}
765
+
766
+
for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
767
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, i);
768
+
data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
769
+
770
+
sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
771
+
SEC_COUNT);
772
+
if (sec_count) {
773
+
DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
774
+
atc_l2_cache_2m_mems[i], sec_count);
775
+
err_data->ce_count += sec_count;
776
+
}
777
+
778
+
ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
779
+
DED_COUNT);
780
+
if (ded_count) {
781
+
DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
782
+
atc_l2_cache_2m_mems[i], ded_count);
783
+
err_data->ue_count += ded_count;
784
+
}
785
+
}
786
+
787
+
for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
788
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, i);
789
+
data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);
790
+
791
+
sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
792
+
SEC_COUNT);
793
+
if (sec_count) {
794
+
DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
795
+
atc_l2_cache_4k_mems[i], sec_count);
796
+
err_data->ce_count += sec_count;
797
+
}
798
+
799
+
ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
800
+
DED_COUNT);
801
+
if (ded_count) {
802
+
DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
803
+
atc_l2_cache_4k_mems[i], ded_count);
804
+
err_data->ue_count += ded_count;
805
+
}
806
+
}
807
+
808
+
WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
809
+
WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
810
+
WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
811
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
812
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
813
+
814
+
return 0;
815
+
}
816
+
817
+
static int gfx_v9_4_ras_error_count(const struct soc15_reg_entry *reg,
818
+
uint32_t se_id, uint32_t inst_id,
819
+
uint32_t value, uint32_t *sec_count,
820
+
uint32_t *ded_count)
821
+
{
822
+
uint32_t i;
823
+
uint32_t sec_cnt, ded_cnt;
824
+
825
+
for (i = 0; i < ARRAY_SIZE(gfx_v9_4_ras_fields); i++) {
826
+
if (gfx_v9_4_ras_fields[i].reg_offset != reg->reg_offset ||
827
+
gfx_v9_4_ras_fields[i].seg != reg->seg ||
828
+
gfx_v9_4_ras_fields[i].inst != reg->inst)
829
+
continue;
830
+
831
+
sec_cnt = (value & gfx_v9_4_ras_fields[i].sec_count_mask) >>
832
+
gfx_v9_4_ras_fields[i].sec_count_shift;
833
+
if (sec_cnt) {
834
+
DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
835
+
gfx_v9_4_ras_fields[i].name, se_id, inst_id,
836
+
sec_cnt);
837
+
*sec_count += sec_cnt;
838
+
}
839
+
840
+
ded_cnt = (value & gfx_v9_4_ras_fields[i].ded_count_mask) >>
841
+
gfx_v9_4_ras_fields[i].ded_count_shift;
842
+
if (ded_cnt) {
843
+
DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",
844
+
gfx_v9_4_ras_fields[i].name, se_id, inst_id,
845
+
ded_cnt);
846
+
*ded_count += ded_cnt;
847
+
}
848
+
}
849
+
850
+
return 0;
851
+
}
852
+
853
+
int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev,
854
+
void *ras_error_status)
855
+
{
856
+
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
857
+
uint32_t sec_count = 0, ded_count = 0;
858
+
uint32_t i, j, k;
859
+
uint32_t reg_value;
860
+
861
+
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
862
+
return -EINVAL;
863
+
864
+
err_data->ue_count = 0;
865
+
err_data->ce_count = 0;
866
+
867
+
mutex_lock(&adev->grbm_idx_mutex);
868
+
869
+
for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {
870
+
for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {
871
+
for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
872
+
k++) {
873
+
gfx_v9_4_select_se_sh(adev, j, 0, k);
874
+
reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
875
+
gfx_v9_4_edc_counter_regs[i]));
876
+
if (reg_value)
877
+
gfx_v9_4_ras_error_count(
878
+
&gfx_v9_4_edc_counter_regs[i],
879
+
j, k, reg_value, &sec_count,
880
+
&ded_count);
881
+
}
882
+
}
883
+
}
884
+
885
+
err_data->ce_count += sec_count;
886
+
err_data->ue_count += ded_count;
887
+
888
+
gfx_v9_4_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
889
+
mutex_unlock(&adev->grbm_idx_mutex);
890
+
891
+
gfx_v9_4_query_utc_edc_status(adev, err_data);
892
+
893
+
return 0;
894
+
}
895
+
896
+
void gfx_v9_4_clear_ras_edc_counter(struct amdgpu_device *adev)
897
+
{
898
+
int i, j, k;
899
+
900
+
mutex_lock(&adev->grbm_idx_mutex);
901
+
for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {
902
+
for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {
903
+
for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
904
+
k++) {
905
+
gfx_v9_4_select_se_sh(adev, j, 0x0, k);
906
+
RREG32(SOC15_REG_ENTRY_OFFSET(
907
+
gfx_v9_4_edc_counter_regs[i]));
908
+
}
909
+
}
910
+
}
911
+
WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
912
+
mutex_unlock(&adev->grbm_idx_mutex);
913
+
914
+
WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
915
+
WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0);
916
+
WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
917
+
WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0);
918
+
WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
919
+
WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0);
920
+
921
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
922
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
923
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
924
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
925
+
926
+
for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
927
+
WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, i);
928
+
RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);
929
+
}
930
+
931
+
for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
932
+
WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, i);
933
+
RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);
934
+
}
935
+
936
+
for (i = 0; i < ARRAY_SIZE(utcl2_router_mems); i++) {
937
+
WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, i);
938
+
RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);
939
+
}
940
+
941
+
for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
942
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, i);
943
+
RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
944
+
}
945
+
946
+
for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
947
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, i);
948
+
RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);
949
+
}
950
+
951
+
WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
952
+
WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
953
+
WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
954
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
955
+
WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
956
+
}
957
+
958
+
int gfx_v9_4_ras_error_inject(struct amdgpu_device *adev, void *inject_if)
959
+
{
960
+
struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
961
+
int ret;
962
+
struct ta_ras_trigger_error_input block_info = { 0 };
963
+
964
+
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
965
+
return -EINVAL;
966
+
967
+
block_info.block_id = info->head.block;
968
+
block_info.sub_block_index = info->head.sub_block_index;
969
+
block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
970
+
block_info.address = info->address;
971
+
block_info.value = info->value;
972
+
973
+
mutex_lock(&adev->grbm_idx_mutex);
974
+
ret = psp_ras_trigger_error(&adev->psp, &block_info);
975
+
mutex_unlock(&adev->grbm_idx_mutex);
976
+
977
+
return ret;
978
+
}
+35
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.h
+35
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.h
···
1
+
/*
2
+
* Copyright 2020 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#ifndef __GFX_V9_4_H__
25
+
#define __GFX_V9_4_H__
26
+
27
+
void gfx_v9_4_clear_ras_edc_counter(struct amdgpu_device *adev);
28
+
29
+
int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev,
30
+
void *ras_error_status);
31
+
32
+
int gfx_v9_4_ras_error_inject(struct amdgpu_device *adev,
33
+
void *inject_if);
34
+
35
+
#endif /* __GFX_V9_4_H__ */