tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

s390/ap: adjust whitespace

Adjust indentation of inline assemblies, so all comments
start at the same position.

Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>

authored by

Heiko Carstens and committed by
Vasily Gorbik a7e196f5 2d6c0008

+23 -23
+23 -23
arch/s390/include/asm/ap.h
··· 60 60 unsigned long reg1 = 0; 61 61 62 62 asm volatile( 63 - " lgr 0,%[reg0]\n" /* qid into gr0 */ 64 - " lghi 1,0\n" /* 0 into gr1 */ 65 - " lghi 2,0\n" /* 0 into gr2 */ 63 + " lgr 0,%[reg0]\n" /* qid into gr0 */ 64 + " lghi 1,0\n" /* 0 into gr1 */ 65 + " lghi 2,0\n" /* 0 into gr2 */ 66 66 " .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */ 67 - "0: la %[reg1],1\n" /* 1 into reg1 */ 67 + "0: la %[reg1],1\n" /* 1 into reg1 */ 68 68 "1:\n" 69 69 EX_TABLE(0b, 1b) 70 70 : [reg1] "+&d" (reg1) ··· 86 86 unsigned long reg2; 87 87 88 88 asm volatile( 89 - " lgr 0,%[qid]\n" /* qid into gr0 */ 90 - " lghi 2,0\n" /* 0 into gr2 */ 89 + " lgr 0,%[qid]\n" /* qid into gr0 */ 90 + " lghi 2,0\n" /* 0 into gr2 */ 91 91 " .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */ 92 - " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 93 - " lgr %[reg2],2\n" /* gr2 into reg2 */ 92 + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 93 + " lgr %[reg2],2\n" /* gr2 into reg2 */ 94 94 : [reg1] "=&d" (reg1), [reg2] "=&d" (reg2) 95 95 : [qid] "d" (qid) 96 96 : "cc", "0", "1", "2"); ··· 128 128 struct ap_queue_status reg1; 129 129 130 130 asm volatile( 131 - " lgr 0,%[reg0]\n" /* qid arg into gr0 */ 131 + " lgr 0,%[reg0]\n" /* qid arg into gr0 */ 132 132 " .insn rre,0xb2af0000,0,0\n" /* PQAP(RAPQ) */ 133 - " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 133 + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 134 134 : [reg1] "=&d" (reg1) 135 135 : [reg0] "d" (reg0) 136 136 : "cc", "0", "1"); ··· 149 149 struct ap_queue_status reg1; 150 150 151 151 asm volatile( 152 - " lgr 0,%[reg0]\n" /* qid arg into gr0 */ 152 + " lgr 0,%[reg0]\n" /* qid arg into gr0 */ 153 153 " .insn rre,0xb2af0000,0,0\n" /* PQAP(ZAPQ) */ 154 - " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 154 + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 155 155 : [reg1] "=&d" (reg1) 156 156 : [reg0] "d" (reg0) 157 157 : "cc", "0", "1"); ··· 190 190 struct ap_config_info *reg2 = config; 191 191 192 192 asm volatile( 193 - " lgr 0,%[reg0]\n" /* QCI fc into gr0 */ 194 - " lgr 2,%[reg2]\n" /* ptr to config into gr2 */ 193 + " lgr 0,%[reg0]\n" /* QCI fc into gr0 */ 194 + " lgr 2,%[reg2]\n" /* ptr to config into gr2 */ 195 195 " .insn rre,0xb2af0000,0,0\n" /* PQAP(QCI) */ 196 - "0: la %[reg1],0\n" /* good case, QCI fc available */ 196 + "0: la %[reg1],0\n" /* good case, QCI fc available */ 197 197 "1:\n" 198 198 EX_TABLE(0b, 1b) 199 199 : [reg1] "+&d" (reg1) ··· 246 246 reg1.qirqctrl = qirqctrl; 247 247 248 248 asm volatile( 249 - " lgr 0,%[reg0]\n" /* qid param into gr0 */ 250 - " lgr 1,%[reg1]\n" /* irq ctrl into gr1 */ 251 - " lgr 2,%[reg2]\n" /* ni addr into gr2 */ 249 + " lgr 0,%[reg0]\n" /* qid param into gr0 */ 250 + " lgr 1,%[reg1]\n" /* irq ctrl into gr1 */ 251 + " lgr 2,%[reg2]\n" /* ni addr into gr2 */ 252 252 " .insn rre,0xb2af0000,0,0\n" /* PQAP(AQIC) */ 253 - " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 253 + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 254 254 : [reg1] "+&d" (reg1) 255 255 : [reg0] "d" (reg0), [reg2] "d" (reg2) 256 256 : "cc", "0", "1", "2"); ··· 297 297 reg1.value = apinfo->val; 298 298 299 299 asm volatile( 300 - " lgr 0,%[reg0]\n" /* qid param into gr0 */ 301 - " lgr 1,%[reg1]\n" /* qact in info into gr1 */ 300 + " lgr 0,%[reg0]\n" /* qid param into gr0 */ 301 + " lgr 1,%[reg1]\n" /* qact in info into gr1 */ 302 302 " .insn rre,0xb2af0000,0,0\n" /* PQAP(QACT) */ 303 - " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 304 - " lgr %[reg2],2\n" /* qact out info into reg2 */ 303 + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 304 + " lgr %[reg2],2\n" /* qact out info into reg2 */ 305 305 : [reg1] "+&d" (reg1), [reg2] "=&d" (reg2) 306 306 : [reg0] "d" (reg0) 307 307 : "cc", "0", "1", "2");