ASoC: WM8994: Don't disable the AIF[1|2]CLK_ENA unconditionaly

Since we began using the late clock disable functionality, ensure that
we don't disable the clock if any of the ADC or DAC paths are still
enabled. This happens when we have simultaneous playback and recording.

Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org

authored by Dimitris Papastamos and committed by Mark Brown a3cff81a 3ee845ac

+19 -6
+19 -6
sound/soc/codecs/wm8994.c
··· 110 111 unsigned int aif1clk_enable:1; 112 unsigned int aif2clk_enable:1; 113 }; 114 115 static int wm8994_readable(unsigned int reg) ··· 1018 1019 switch (event) { 1020 case SND_SOC_DAPM_PRE_PMU: 1021 - if (wm8994->aif1clk_enable) 1022 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1023 WM8994_AIF1CLK_ENA_MASK, 1024 WM8994_AIF1CLK_ENA); 1025 - if (wm8994->aif2clk_enable) 1026 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1027 WM8994_AIF2CLK_ENA_MASK, 1028 WM8994_AIF2CLK_ENA); 1029 break; 1030 } 1031 ··· 1044 1045 switch (event) { 1046 case SND_SOC_DAPM_POST_PMD: 1047 - if (wm8994->aif1clk_enable) { 1048 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1049 WM8994_AIF1CLK_ENA_MASK, 0); 1050 - wm8994->aif1clk_enable = 0; 1051 } 1052 - if (wm8994->aif2clk_enable) { 1053 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1054 WM8994_AIF2CLK_ENA_MASK, 0); 1055 - wm8994->aif2clk_enable = 0; 1056 } 1057 break; 1058 } ··· 1070 case SND_SOC_DAPM_PRE_PMU: 1071 wm8994->aif1clk_enable = 1; 1072 break; 1073 } 1074 1075 return 0; ··· 1087 switch (event) { 1088 case SND_SOC_DAPM_PRE_PMU: 1089 wm8994->aif2clk_enable = 1; 1090 break; 1091 } 1092
··· 110 111 unsigned int aif1clk_enable:1; 112 unsigned int aif2clk_enable:1; 113 + 114 + unsigned int aif1clk_disable:1; 115 + unsigned int aif2clk_disable:1; 116 }; 117 118 static int wm8994_readable(unsigned int reg) ··· 1015 1016 switch (event) { 1017 case SND_SOC_DAPM_PRE_PMU: 1018 + if (wm8994->aif1clk_enable) { 1019 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1020 WM8994_AIF1CLK_ENA_MASK, 1021 WM8994_AIF1CLK_ENA); 1022 + wm8994->aif1clk_enable = 0; 1023 + } 1024 + if (wm8994->aif2clk_enable) { 1025 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1026 WM8994_AIF2CLK_ENA_MASK, 1027 WM8994_AIF2CLK_ENA); 1028 + wm8994->aif2clk_enable = 0; 1029 + } 1030 break; 1031 } 1032 ··· 1037 1038 switch (event) { 1039 case SND_SOC_DAPM_POST_PMD: 1040 + if (wm8994->aif1clk_disable) { 1041 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1042 WM8994_AIF1CLK_ENA_MASK, 0); 1043 + wm8994->aif1clk_disable = 0; 1044 } 1045 + if (wm8994->aif2clk_disable) { 1046 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1047 WM8994_AIF2CLK_ENA_MASK, 0); 1048 + wm8994->aif2clk_disable = 0; 1049 } 1050 break; 1051 } ··· 1063 case SND_SOC_DAPM_PRE_PMU: 1064 wm8994->aif1clk_enable = 1; 1065 break; 1066 + case SND_SOC_DAPM_POST_PMD: 1067 + wm8994->aif1clk_disable = 1; 1068 + break; 1069 } 1070 1071 return 0; ··· 1077 switch (event) { 1078 case SND_SOC_DAPM_PRE_PMU: 1079 wm8994->aif2clk_enable = 1; 1080 + break; 1081 + case SND_SOC_DAPM_POST_PMD: 1082 + wm8994->aif2clk_disable = 1; 1083 break; 1084 } 1085