ASoC: WM8994: Don't disable the AIF[1|2]CLK_ENA unconditionaly

Since we began using the late clock disable functionality, ensure that
we don't disable the clock if any of the ADC or DAC paths are still
enabled. This happens when we have simultaneous playback and recording.

Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org

authored by Dimitris Papastamos and committed by Mark Brown a3cff81a 3ee845ac

+19 -6
+19 -6
sound/soc/codecs/wm8994.c
··· 110 110 111 111 unsigned int aif1clk_enable:1; 112 112 unsigned int aif2clk_enable:1; 113 + 114 + unsigned int aif1clk_disable:1; 115 + unsigned int aif2clk_disable:1; 113 116 }; 114 117 115 118 static int wm8994_readable(unsigned int reg) ··· 1018 1015 1019 1016 switch (event) { 1020 1017 case SND_SOC_DAPM_PRE_PMU: 1021 - if (wm8994->aif1clk_enable) 1018 + if (wm8994->aif1clk_enable) { 1022 1019 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1023 1020 WM8994_AIF1CLK_ENA_MASK, 1024 1021 WM8994_AIF1CLK_ENA); 1025 - if (wm8994->aif2clk_enable) 1022 + wm8994->aif1clk_enable = 0; 1023 + } 1024 + if (wm8994->aif2clk_enable) { 1026 1025 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1027 1026 WM8994_AIF2CLK_ENA_MASK, 1028 1027 WM8994_AIF2CLK_ENA); 1028 + wm8994->aif2clk_enable = 0; 1029 + } 1029 1030 break; 1030 1031 } 1031 1032 ··· 1044 1037 1045 1038 switch (event) { 1046 1039 case SND_SOC_DAPM_POST_PMD: 1047 - if (wm8994->aif1clk_enable) { 1040 + if (wm8994->aif1clk_disable) { 1048 1041 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 1049 1042 WM8994_AIF1CLK_ENA_MASK, 0); 1050 - wm8994->aif1clk_enable = 0; 1043 + wm8994->aif1clk_disable = 0; 1051 1044 } 1052 - if (wm8994->aif2clk_enable) { 1045 + if (wm8994->aif2clk_disable) { 1053 1046 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 1054 1047 WM8994_AIF2CLK_ENA_MASK, 0); 1055 - wm8994->aif2clk_enable = 0; 1048 + wm8994->aif2clk_disable = 0; 1056 1049 } 1057 1050 break; 1058 1051 } ··· 1070 1063 case SND_SOC_DAPM_PRE_PMU: 1071 1064 wm8994->aif1clk_enable = 1; 1072 1065 break; 1066 + case SND_SOC_DAPM_POST_PMD: 1067 + wm8994->aif1clk_disable = 1; 1068 + break; 1073 1069 } 1074 1070 1075 1071 return 0; ··· 1087 1077 switch (event) { 1088 1078 case SND_SOC_DAPM_PRE_PMU: 1089 1079 wm8994->aif2clk_enable = 1; 1080 + break; 1081 + case SND_SOC_DAPM_POST_PMD: 1082 + wm8994->aif2clk_disable = 1; 1090 1083 break; 1091 1084 } 1092 1085