Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

USB: io_edgeport: checkpatch cleanups

Minor whitespace cleanups to make checkpatch happy.

Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

+141 -145
+8 -8
drivers/usb/serial/io_edgeport.h
··· 34 34 35 35 36 36 37 - /* The following table is used to map the USBx port number to 37 + /* The following table is used to map the USBx port number to 38 38 * the device serial number (or physical USB path), */ 39 39 #define MAX_EDGEPORTS 64 40 40 41 41 struct comMapper { 42 42 char SerialNumber[MAX_SERIALNUMBER_LEN+1]; /* Serial number/usb path */ 43 - int numPorts; /* Number of ports */ 44 - int Original[MAX_RS232_PORTS]; /* Port numbers set by IOCTL */ 45 - int Port[MAX_RS232_PORTS]; /* Actual used port numbers */ 43 + int numPorts; /* Number of ports */ 44 + int Original[MAX_RS232_PORTS]; /* Port numbers set by IOCTL */ 45 + int Port[MAX_RS232_PORTS]; /* Actual used port numbers */ 46 46 }; 47 47 48 48 ··· 51 51 /* /proc/edgeport Interface 52 52 * This interface uses read/write/lseek interface to talk to the edgeport driver 53 53 * the following read functions are supported: */ 54 - #define PROC_GET_MAPPING_TO_PATH 1 54 + #define PROC_GET_MAPPING_TO_PATH 1 55 55 #define PROC_GET_COM_ENTRY 2 56 56 #define PROC_GET_EDGE_MANUF_DESCRIPTOR 3 57 57 #define PROC_GET_BOOT_DESCRIPTOR 4 ··· 64 64 65 65 66 66 /* the following write functions are supported: */ 67 - #define PROC_SET_COM_MAPPING 1 67 + #define PROC_SET_COM_MAPPING 1 68 68 #define PROC_SET_COM_ENTRY 2 69 69 70 70 ··· 97 97 __u8 BoardRev; /* PCB revision level (chg only if s/w visible) */ 98 98 99 99 __u8 BootMajorVersion; /* Boot Firmware version: xx. */ 100 - __u8 BootMinorVersion; /* yy. */ 101 - __le16 BootBuildNumber; /* zzzz (LE format) */ 100 + __u8 BootMinorVersion; /* yy. */ 101 + __le16 BootBuildNumber; /* zzzz (LE format) */ 102 102 103 103 __u8 FirmwareMajorVersion; /* Operational Firmware version:xx. */ 104 104 __u8 FirmwareMinorVersion; /* yy. */
+48 -47
drivers/usb/serial/io_ionsp.h
··· 89 89 // 90 90 91 91 struct int_status_pkt { 92 - __u16 RxBytesAvail; // Additional bytes available to 93 - // be read from Bulk IN pipe 94 - __u16 TxCredits[ MAX_RS232_PORTS ]; // Additional space available in 95 - // given port's TxBuffer 92 + __u16 RxBytesAvail; // Additional bytes available to 93 + // be read from Bulk IN pipe 94 + __u16 TxCredits[MAX_RS232_PORTS]; // Additional space available in 95 + // given port's TxBuffer 96 96 }; 97 97 98 98 ··· 115 115 #define IOSP_CMD_STAT_BIT 0x80 // If set, this is command/status header 116 116 117 117 #define IS_CMD_STAT_HDR(Byte1) ((Byte1) & IOSP_CMD_STAT_BIT) 118 - #define IS_DATA_HDR(Byte1) (! IS_CMD_STAT_HDR(Byte1)) 118 + #define IS_DATA_HDR(Byte1) (!IS_CMD_STAT_HDR(Byte1)) 119 119 120 120 #define IOSP_GET_HDR_PORT(Byte1) ((__u8) ((Byte1) & IOSP_PORT_MASK)) 121 - #define IOSP_GET_HDR_DATA_LEN(Byte1, Byte2) ((__u16) ( ((__u16)((Byte1) & 0x78)) << 5) | (Byte2)) 121 + #define IOSP_GET_HDR_DATA_LEN(Byte1, Byte2) ((__u16) (((__u16)((Byte1) & 0x78)) << 5) | (Byte2)) 122 122 #define IOSP_GET_STATUS_CODE(Byte1) ((__u8) (((Byte1) & 0x78) >> 3)) 123 123 124 124 125 125 // 126 126 // These macros build the 1st and 2nd bytes for a data header 127 127 // 128 - #define IOSP_BUILD_DATA_HDR1(Port, Len) ((__u8) (((Port) | ((__u8) (((__u16) (Len)) >> 5) & 0x78 )))) 128 + #define IOSP_BUILD_DATA_HDR1(Port, Len) ((__u8) (((Port) | ((__u8) (((__u16) (Len)) >> 5) & 0x78)))) 129 129 #define IOSP_BUILD_DATA_HDR2(Port, Len) ((__u8) (Len)) 130 130 131 131 132 132 // 133 133 // These macros build the 1st and 2nd bytes for a command header 134 134 // 135 - #define IOSP_BUILD_CMD_HDR1(Port, Cmd) ((__u8) ( IOSP_CMD_STAT_BIT | (Port) | ((__u8) ((Cmd) << 3)) )) 135 + #define IOSP_BUILD_CMD_HDR1(Port, Cmd) ((__u8) (IOSP_CMD_STAT_BIT | (Port) | ((__u8) ((Cmd) << 3)))) 136 136 137 137 138 138 //-------------------------------------------------------------- ··· 194 194 // Define macros to simplify building of IOSP cmds 195 195 // 196 196 197 - #define MAKE_CMD_WRITE_REG(ppBuf, pLen, Port, Reg, Val) \ 198 - do { \ 199 - (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1( (Port), IOSP_WRITE_UART_REG(Reg) ); \ 200 - (*(ppBuf))[1] = (Val); \ 201 - \ 202 - *ppBuf += 2; \ 203 - *pLen += 2; \ 204 - } while (0) 197 + #define MAKE_CMD_WRITE_REG(ppBuf, pLen, Port, Reg, Val) \ 198 + do { \ 199 + (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), \ 200 + IOSP_WRITE_UART_REG(Reg)); \ 201 + (*(ppBuf))[1] = (Val); \ 202 + \ 203 + *ppBuf += 2; \ 204 + *pLen += 2; \ 205 + } while (0) 205 206 206 - #define MAKE_CMD_EXT_CMD(ppBuf, pLen, Port, ExtCmd, Param) \ 207 - do { \ 208 - (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1( (Port), IOSP_EXT_CMD ); \ 209 - (*(ppBuf))[1] = (ExtCmd); \ 210 - (*(ppBuf))[2] = (Param); \ 211 - \ 212 - *ppBuf += 3; \ 213 - *pLen += 3; \ 214 - } while (0) 207 + #define MAKE_CMD_EXT_CMD(ppBuf, pLen, Port, ExtCmd, Param) \ 208 + do { \ 209 + (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), IOSP_EXT_CMD); \ 210 + (*(ppBuf))[1] = (ExtCmd); \ 211 + (*(ppBuf))[2] = (Param); \ 212 + \ 213 + *ppBuf += 3; \ 214 + *pLen += 3; \ 215 + } while (0) 215 216 216 217 217 218 ··· 311 310 // 312 311 // IOSP_CMD_RX_CHECK_REQ 313 312 // 314 - // This command is used to assist in the implementation of the 315 - // IOCTL_SERIAL_PURGE Windows IOCTL. 316 - // This IOSP command tries to place a marker at the end of the RX 317 - // queue in the Edgeport. If the Edgeport RX queue is full then 318 - // the Check will be discarded. 319 - // It is up to the device driver to timeout waiting for the 320 - // RX_CHECK_RSP. If a RX_CHECK_RSP is received, the driver is 321 - // sure that all data has been received from the edgeport and 313 + // This command is used to assist in the implementation of the 314 + // IOCTL_SERIAL_PURGE Windows IOCTL. 315 + // This IOSP command tries to place a marker at the end of the RX 316 + // queue in the Edgeport. If the Edgeport RX queue is full then 317 + // the Check will be discarded. 318 + // It is up to the device driver to timeout waiting for the 319 + // RX_CHECK_RSP. If a RX_CHECK_RSP is received, the driver is 320 + // sure that all data has been received from the edgeport and 322 321 // may now purge any internal RX buffers. 323 - // Note tat the sequence numbers may be used to detect lost 322 + // Note tat the sequence numbers may be used to detect lost 324 323 // CHECK_REQs. 325 324 326 325 // Example for Port 0 ··· 342 341 // 343 342 // 1ssssPPP P1P1P1P1 [ P2P2P2P2P2 ]... 344 343 // 345 - // ssss: 00-07 2-byte status. ssss identifies which UART register 344 + // ssss: 00-07 2-byte status. ssss identifies which UART register 346 345 // has changed value, and the new value is in P1. 347 346 // Note that the ssss values do not correspond to the 348 347 // 16554 register numbers given in 16554.H. Instead, ··· 384 383 // returns this in order to report 385 384 // changes in modem status lines 386 385 // (CTS, DSR, RI, CD) 387 - // 386 + // 388 387 389 388 // 0x02 // Available for future expansion 390 - // 0x03 // 391 - // 0x04 // 392 - // 0x05 // 393 - // 0x06 // 394 - // 0x07 // 389 + // 0x03 // 390 + // 0x04 // 391 + // 0x05 // 392 + // 0x06 // 393 + // 0x07 // 395 394 396 395 397 396 /**************************************************** ··· 401 400 #define IOSP_STATUS_LSR_DATA 0x08 // P1 is new value of LSR register (same as STATUS_LSR) 402 401 403 402 // P2 is errored character read from 404 - // RxFIFO after LSR reported an error. 403 + // RxFIFO after LSR reported an error. 405 404 406 405 #define IOSP_EXT_STATUS 0x09 // P1 is status/response code, param in P2. 407 406 ··· 409 408 // Response Codes (P1 values) for 3-byte status messages 410 409 411 410 #define IOSP_EXT_STATUS_CHASE_RSP 0 // Reply to CHASE_PORT cmd. P2 is outcome: 412 - #define IOSP_EXT_STATUS_CHASE_PASS 0 // P2 = 0: All Tx data drained successfully 411 + #define IOSP_EXT_STATUS_CHASE_PASS 0 // P2 = 0: All Tx data drained successfully 413 412 #define IOSP_EXT_STATUS_CHASE_FAIL 1 // P2 = 1: Timed out (stuck due to flow 414 413 415 414 // control from remote device). ··· 447 446 // Macros to parse status messages 448 447 // 449 448 450 - #define IOSP_GET_STATUS_LEN(code) ( (code) < 8 ? 2 : ((code) < 0x0A ? 3 : 4) ) 449 + #define IOSP_GET_STATUS_LEN(code) ((code) < 8 ? 2 : ((code) < 0x0A ? 3 : 4)) 451 450 452 - #define IOSP_STATUS_IS_2BYTE(code) ( (code) < 0x08 ) 453 - #define IOSP_STATUS_IS_3BYTE(code) ( ((code) >= 0x08) && ((code) <= 0x0B) ) 454 - #define IOSP_STATUS_IS_4BYTE(code) ( ((code) >= 0x0C) && ((code) <= 0x0D) ) 451 + #define IOSP_STATUS_IS_2BYTE(code) ((code) < 0x08) 452 + #define IOSP_STATUS_IS_3BYTE(code) (((code) >= 0x08) && ((code) <= 0x0B)) 453 + #define IOSP_STATUS_IS_4BYTE(code) (((code) >= 0x0C) && ((code) <= 0x0D)) 455 454
+47 -41
drivers/usb/serial/io_ti.h
··· 1 - /***************************************************************************** 1 + /***************************************************************************** 2 2 * 3 3 * Copyright (C) 1997-2002 Inside Out Networks, Inc. 4 4 * ··· 22 22 #define DTK_ADDR_SPACE_I2C_TYPE_II 0x82 /* Addr is placed in I2C area */ 23 23 #define DTK_ADDR_SPACE_I2C_TYPE_III 0x83 /* Addr is placed in I2C area */ 24 24 25 - // UART Defines 26 - #define UMPMEM_BASE_UART1 0xFFA0 /* UMP UART1 base address */ 27 - #define UMPMEM_BASE_UART2 0xFFB0 /* UMP UART2 base address */ 28 - #define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */ 25 + /* UART Defines */ 26 + #define UMPMEM_BASE_UART1 0xFFA0 /* UMP UART1 base address */ 27 + #define UMPMEM_BASE_UART2 0xFFB0 /* UMP UART2 base address */ 28 + #define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */ 29 29 30 30 /* Bits per character */ 31 31 #define UMP_UART_CHAR5BITS 0x00 ··· 54 54 #define UMP_UART_LSR_RX_MASK 0x10 55 55 #define UMP_UART_LSR_TX_MASK 0x20 56 56 57 - #define UMP_UART_LSR_DATA_MASK ( LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK ) 57 + #define UMP_UART_LSR_DATA_MASK (LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK) 58 58 59 59 /* Port Settings Constants) */ 60 60 #define UMP_MASK_UART_FLAGS_RTS_FLOW 0x0001 ··· 79 79 #define UMP_PORT_DIR_OUT 0x01 80 80 #define UMP_PORT_DIR_IN 0x02 81 81 82 - // Address of Port 0 83 - #define UMPM_UART1_PORT 0x03 82 + /* Address of Port 0 */ 83 + #define UMPM_UART1_PORT 0x03 84 84 85 - // Commands 86 - #define UMPC_SET_CONFIG 0x05 87 - #define UMPC_OPEN_PORT 0x06 88 - #define UMPC_CLOSE_PORT 0x07 89 - #define UMPC_START_PORT 0x08 90 - #define UMPC_STOP_PORT 0x09 91 - #define UMPC_TEST_PORT 0x0A 92 - #define UMPC_PURGE_PORT 0x0B 85 + /* Commands */ 86 + #define UMPC_SET_CONFIG 0x05 87 + #define UMPC_OPEN_PORT 0x06 88 + #define UMPC_CLOSE_PORT 0x07 89 + #define UMPC_START_PORT 0x08 90 + #define UMPC_STOP_PORT 0x09 91 + #define UMPC_TEST_PORT 0x0A 92 + #define UMPC_PURGE_PORT 0x0B 93 93 94 - #define UMPC_COMPLETE_READ 0x80 // Force the Firmware to complete the current Read 95 - #define UMPC_HARDWARE_RESET 0x81 // Force UMP back into BOOT Mode 96 - #define UMPC_COPY_DNLD_TO_I2C 0x82 // Copy current download image to type 0xf2 record in 16k I2C 97 - // firmware will change 0xff record to type 2 record when complete 94 + /* Force the Firmware to complete the current Read */ 95 + #define UMPC_COMPLETE_READ 0x80 96 + /* Force UMP back into BOOT Mode */ 97 + #define UMPC_HARDWARE_RESET 0x81 98 + /* 99 + * Copy current download image to type 0xf2 record in 16k I2C 100 + * firmware will change 0xff record to type 2 record when complete 101 + */ 102 + #define UMPC_COPY_DNLD_TO_I2C 0x82 98 103 99 - // Special function register commands 100 - // wIndex is register address 101 - // wValue is MSB/LSB mask/data 102 - #define UMPC_WRITE_SFR 0x83 // Write SFR Register 104 + /* 105 + * Special function register commands 106 + * wIndex is register address 107 + * wValue is MSB/LSB mask/data 108 + */ 109 + #define UMPC_WRITE_SFR 0x83 /* Write SFR Register */ 103 110 104 - // wIndex is register address 105 - #define UMPC_READ_SFR 0x84 // Read SRF Register 111 + /* wIndex is register address */ 112 + #define UMPC_READ_SFR 0x84 /* Read SRF Register */ 106 113 107 - // Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port) 114 + /* Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port) */ 108 115 #define UMPC_SET_CLR_DTR 0x85 109 116 110 - // Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port) 117 + /* Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port) */ 111 118 #define UMPC_SET_CLR_RTS 0x86 112 119 113 - // Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) 120 + /* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */ 114 121 #define UMPC_SET_CLR_LOOPBACK 0x87 115 122 116 - // Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port) 123 + /* Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */ 117 124 #define UMPC_SET_CLR_BREAK 0x88 118 125 119 - // Read MSR wIndex ModuleID (port) 126 + /* Read MSR wIndex ModuleID (port) */ 120 127 #define UMPC_READ_MSR 0x89 121 128 122 - /* Toolkit commands */ 123 - /* Read-write group */ 124 - #define UMPC_MEMORY_READ 0x92 125 - #define UMPC_MEMORY_WRITE 0x93 129 + /* Toolkit commands */ 130 + /* Read-write group */ 131 + #define UMPC_MEMORY_READ 0x92 132 + #define UMPC_MEMORY_WRITE 0x93 126 133 127 134 /* 128 135 * UMP DMA Definitions ··· 137 130 #define UMPD_OEDB1_ADDRESS 0xFF08 138 131 #define UMPD_OEDB2_ADDRESS 0xFF10 139 132 140 - struct out_endpoint_desc_block 141 - { 133 + struct out_endpoint_desc_block { 142 134 __u8 Configuration; 143 135 __u8 XBufAddr; 144 136 __u8 XByteCount; ··· 153 147 * TYPE DEFINITIONS 154 148 * Structures for Firmware commands 155 149 */ 156 - struct ump_uart_config /* UART settings */ 157 - { 150 + /* UART settings */ 151 + struct ump_uart_config { 158 152 __u16 wBaudRate; /* Baud rate */ 159 153 __u16 wFlags; /* Bitmap mask of flags */ 160 154 __u8 bDataBits; /* 5..8 - data bits per character */ ··· 171 165 * TYPE DEFINITIONS 172 166 * Structures for USB interrupts 173 167 */ 174 - struct ump_interrupt /* Interrupt packet structure */ 175 - { 168 + /* Interrupt packet structure */ 169 + struct ump_interrupt { 176 170 __u8 bICode; /* Interrupt code (interrupt num) */ 177 171 __u8 bIInfo; /* Interrupt information */ 178 172 } __attribute__((packed));
+38 -49
drivers/usb/serial/io_usbvend.h
··· 26 26 27 27 // 28 28 // Definitions of USB product IDs 29 - // 29 + // 30 30 31 31 #define USB_VENDOR_ID_ION 0x1608 // Our VID 32 32 #define USB_VENDOR_ID_TI 0x0451 // TI VID ··· 54 54 // Product IDs - assigned to match middle digit of serial number (No longer true) 55 55 56 56 #define ION_DEVICE_ID_80251_NETCHIP 0x020 // This bit is set in the PID if this edgeport hardware$ 57 - // is based on the 80251+Netchip. 57 + // is based on the 80251+Netchip. 58 58 59 59 #define ION_DEVICE_ID_GENERATION_1 0x00 // Value for 930 based edgeports 60 60 #define ION_DEVICE_ID_GENERATION_2 0x01 // Value for 80251+Netchip. ··· 134 134 #define ION_DEVICE_ID_TI_EDGEPORT_416 0x0212 // Edgeport/416 135 135 #define ION_DEVICE_ID_TI_EDGEPORT_1 0x0215 // Edgeport/1 RS232 136 136 #define ION_DEVICE_ID_TI_EDGEPORT_42 0x0217 // Edgeport/42 4 hub 2 RS232 137 - #define ION_DEVICE_ID_TI_EDGEPORT_22I 0x021A // Edgeport/22I is an Edgeport/4 with ports 1&2 RS422 and ports 3&4 RS232 137 + #define ION_DEVICE_ID_TI_EDGEPORT_22I 0x021A // Edgeport/22I is an Edgeport/4 with ports 1&2 RS422 and ports 3&4 RS232 138 138 #define ION_DEVICE_ID_TI_EDGEPORT_2C 0x021B // Edgeport/2c RS232 139 139 #define ION_DEVICE_ID_TI_EDGEPORT_221C 0x021C // Edgeport/221c is a TI based Edgeport/2 with lucent chip and 140 140 // 2 external hub ports - Large I2C ··· 142 142 // 2 external hub ports - Large I2C 143 143 #define ION_DEVICE_ID_TI_EDGEPORT_21C 0x021E // Edgeport/21c is a TI based Edgeport/2 with lucent chip 144 144 145 - // Generation 3 devices -- 3410 based edgport/1 (256 byte I2C) 145 + // Generation 3 devices -- 3410 based edgport/1 (256 byte I2C) 146 146 #define ION_DEVICE_ID_TI_TI3410_EDGEPORT_1 0x0240 // Edgeport/1 RS232 147 147 #define ION_DEVICE_ID_TI_TI3410_EDGEPORT_1I 0x0241 // Edgeport/1i- RS422 model 148 148 ··· 176 176 // Default to /P function 177 177 178 178 #define ION_DEVICE_ID_PLUS_PWR_HP4CD 0x30C // 5052 Plus Power HubPort/4CD+ (for Dell) 179 - #define ION_DEVICE_ID_PLUS_PWR_HP4C 0x30D // 5052 Plus Power HubPort/4C+ 179 + #define ION_DEVICE_ID_PLUS_PWR_HP4C 0x30D // 5052 Plus Power HubPort/4C+ 180 180 #define ION_DEVICE_ID_PLUS_PWR_PCI 0x30E // 3410 Plus Power PCI Host Controller 4 port 181 181 182 182 ··· 217 217 #define ION_DEVICE_ID_MT4X56USB 0x1403 // OEM device 218 218 219 219 220 - #define GENERATION_ID_FROM_USB_PRODUCT_ID( ProductId ) \ 221 - ( (__u16) ((ProductId >> 8) & (ION_GENERATION_MASK)) ) 220 + #define GENERATION_ID_FROM_USB_PRODUCT_ID(ProductId) \ 221 + ((__u16) ((ProductId >> 8) & (ION_GENERATION_MASK))) 222 222 223 - #define MAKE_USB_PRODUCT_ID( OemId, DeviceId ) \ 224 - ( (__u16) (((OemId) << 10) || (DeviceId)) ) 223 + #define MAKE_USB_PRODUCT_ID(OemId, DeviceId) \ 224 + ((__u16) (((OemId) << 10) || (DeviceId))) 225 225 226 - #define DEVICE_ID_FROM_USB_PRODUCT_ID( ProductId ) \ 227 - ( (__u16) ((ProductId) & (EDGEPORT_DEVICE_ID_MASK)) ) 226 + #define DEVICE_ID_FROM_USB_PRODUCT_ID(ProductId) \ 227 + ((__u16) ((ProductId) & (EDGEPORT_DEVICE_ID_MASK))) 228 228 229 - #define OEM_ID_FROM_USB_PRODUCT_ID( ProductId ) \ 230 - ( (__u16) (((ProductId) >> 10) & 0x3F) ) 229 + #define OEM_ID_FROM_USB_PRODUCT_ID(ProductId) \ 230 + ((__u16) (((ProductId) >> 10) & 0x3F)) 231 231 232 232 // 233 233 // Definitions of parameters for download code. Note that these are ··· 237 237 238 238 // TxCredits value below which driver won't bother sending (to prevent too many small writes). 239 239 // Send only if above 25% 240 - #define EDGE_FW_GET_TX_CREDITS_SEND_THRESHOLD(InitialCredit, MaxPacketSize) (max( ((InitialCredit) / 4), (MaxPacketSize) )) 240 + #define EDGE_FW_GET_TX_CREDITS_SEND_THRESHOLD(InitialCredit, MaxPacketSize) (max(((InitialCredit) / 4), (MaxPacketSize))) 241 241 242 242 #define EDGE_FW_BULK_MAX_PACKET_SIZE 64 // Max Packet Size for Bulk In Endpoint (EP1) 243 243 #define EDGE_FW_BULK_READ_BUFFER_SIZE 1024 // Size to use for Bulk reads ··· 263 263 // wValue = 16-bit address 264 264 // wIndex = unused (though we could put segment 00: or FF: here) 265 265 // wLength = # bytes to read/write (max 64) 266 - // 266 + // 267 267 268 268 #define USB_REQUEST_ION_RESET_DEVICE 0 // Warm reboot Edgeport, retaining USB address 269 269 #define USB_REQUEST_ION_GET_EPIC_DESC 1 // Get Edgeport Compatibility Descriptor ··· 278 278 #define USB_REQUEST_ION_ENABLE_SUSPEND 9 // Enable/Disable suspend feature 279 279 // (wValue != 0: Enable; wValue = 0: Disable) 280 280 281 - #define USB_REQUEST_ION_SEND_IOSP 10 // Send an IOSP command to the edgeport over the control pipe 281 + #define USB_REQUEST_ION_SEND_IOSP 10 // Send an IOSP command to the edgeport over the control pipe 282 282 #define USB_REQUEST_ION_RECV_IOSP 11 // Receive an IOSP command from the edgeport over the control pipe 283 283 284 284 ··· 301 301 // this is a "real" Edgeport. 302 302 // 303 303 304 - struct edge_compatibility_bits 305 - { 304 + struct edge_compatibility_bits { 306 305 // This __u32 defines which Vendor-specific commands/functionality 307 306 // the device supports on the default EP0 pipe. 308 307 ··· 333 334 __u32 TrueEdgeport : 1; // 0001 Set if device is a 'real' Edgeport 334 335 // (Used only by driver, NEVER set by an EPiC device) 335 336 __u32 GenUnused : 31; // Available for future expansion, must be 0 336 - 337 337 }; 338 338 339 339 #define EDGE_COMPATIBILITY_MASK0 0x0001 340 340 #define EDGE_COMPATIBILITY_MASK1 0x3FFF 341 341 #define EDGE_COMPATIBILITY_MASK2 0x0001 342 342 343 - struct edge_compatibility_descriptor 344 - { 343 + struct edge_compatibility_descriptor { 345 344 __u8 Length; // Descriptor Length (per USB spec) 346 345 __u8 DescType; // Descriptor Type (per USB spec, =DEVICE type) 347 346 __u8 EpicVer; // Version of EPiC spec supported 348 - // (Currently must be 1) 347 + // (Currently must be 1) 349 348 __u8 NumPorts; // Number of serial ports supported 350 349 __u8 iDownloadFile; // Index of string containing download code filename 351 - // 0=no download, FF=download compiled into driver. 352 - __u8 Unused[ 3 ]; // Available for future expansion, must be 0 353 - // (Currently must be 0). 350 + // 0=no download, FF=download compiled into driver. 351 + __u8 Unused[3]; // Available for future expansion, must be 0 352 + // (Currently must be 0). 354 353 __u8 MajorVersion; // Firmware version: xx. 355 354 __u8 MinorVersion; // yy. 356 355 __le16 BuildNumber; // zzzz (LE format) ··· 356 359 // The following structure contains __u32s, with each bit 357 360 // specifying whether the EPiC device supports the given 358 361 // command or functionality. 359 - 360 362 struct edge_compatibility_bits Supports; 361 - 362 363 }; 363 364 364 365 // Values for iDownloadFile ··· 386 391 387 392 // Define the max block size that may be read or written 388 393 // in a read/write RAM/ROM command. 389 - #define MAX_SIZE_REQ_ION_READ_MEM ( (__u16) 64 ) 390 - #define MAX_SIZE_REQ_ION_WRITE_MEM ( (__u16) 64 ) 394 + #define MAX_SIZE_REQ_ION_READ_MEM ((__u16)64) 395 + #define MAX_SIZE_REQ_ION_WRITE_MEM ((__u16)64) 391 396 392 397 393 398 // ··· 540 545 __u8 MajorVersion; // C6 Firmware version: xx. 541 546 __u8 MinorVersion; // C7 yy. 542 547 __le16 BuildNumber; // C8 zzzz (LE format) 543 - 548 + 544 549 __u16 EnumRootDescTable; // CA Root of ROM-based descriptor table 545 550 __u8 NumDescTypes; // CC Number of supported descriptor types 546 551 ··· 592 597 #define I2C_DESC_TYPE_ION 0 // Not defined by TI 593 598 594 599 595 - struct ti_i2c_desc 596 - { 600 + struct ti_i2c_desc { 597 601 __u8 Type; // Type of descriptor 598 602 __u16 Size; // Size of data only not including header 599 603 __u8 CheckSum; // Checksum (8 bit sum of data only) 600 604 __u8 Data[0]; // Data starts here 601 - }__attribute__((packed)); 605 + } __attribute__((packed)); 602 606 603 607 // for 5152 devices only (type 2 record) 604 608 // for 3410 the version is stored in the WATCHPORT_FIRMWARE_VERSION descriptor 605 - struct ti_i2c_firmware_rec 606 - { 609 + struct ti_i2c_firmware_rec { 607 610 __u8 Ver_Major; // Firmware Major version number 608 611 __u8 Ver_Minor; // Firmware Minor version number 609 612 __u8 Data[0]; // Download starts here 610 - }__attribute__((packed)); 613 + } __attribute__((packed)); 611 614 612 615 613 - struct watchport_firmware_version 614 - { 616 + struct watchport_firmware_version { 615 617 // Added 2 bytes for version number 616 618 __u8 Version_Major; // Download Version (for Watchport) 617 619 __u8 Version_Minor; 618 - }__attribute__((packed)); 620 + } __attribute__((packed)); 619 621 620 622 621 623 // Structure of header of download image in fw_down.h 622 - struct ti_i2c_image_header 623 - { 624 + struct ti_i2c_image_header { 624 625 __le16 Length; 625 626 __u8 CheckSum; 626 - }__attribute__((packed)); 627 + } __attribute__((packed)); 627 628 628 - struct ti_basic_descriptor 629 - { 629 + struct ti_basic_descriptor { 630 630 __u8 Power; // Self powered 631 631 // bit 7: 1 - power switching supported 632 632 // 0 - power switching not supported ··· 653 663 #define TI_I2C_SIZE_MASK 0x1f // 5 bits 654 664 #define TI_GET_I2C_SIZE(x) ((((x) & TI_I2C_SIZE_MASK)+1)*256) 655 665 656 - #define TI_MAX_I2C_SIZE ( 16 * 1024 ) 666 + #define TI_MAX_I2C_SIZE (16 * 1024) 657 667 658 - #define TI_MANUF_VERSION_0 0 668 + #define TI_MANUF_VERSION_0 0 659 669 660 670 // IonConig2 flags 661 671 #define TI_CONFIG2_RS232 0x01 ··· 666 676 #define TI_CONFIG2_WATCHPORT 0x10 667 677 668 678 669 - struct edge_ti_manuf_descriptor 670 - { 679 + struct edge_ti_manuf_descriptor { 671 680 __u8 IonConfig; // Config byte for ION manufacturing use 672 681 __u8 IonConfig2; // Expansion 673 682 __u8 Version; // Version ··· 677 688 __u8 HubConfig2; // Used to configure the Hub 678 689 __u8 TotalPorts; // Total Number of Com Ports for the entire device (All UMPs) 679 690 __u8 Reserved; // Reserved 680 - }__attribute__((packed)); 691 + } __attribute__((packed)); 681 692 682 693 683 694 #endif // if !defined(_USBVEND_H)