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ARM: at91: remove at91rm9200_sdramc.h
include/soc/at91/at91rm9200_sdramc.h is replaced by
include/linux/mfd/syscon/atmel-smc.h as this is actually a syscon device.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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include/soc/at91/at91rm9200_sdramc.h
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include/soc/at91/at91rm9200_sdramc.h
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/*
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* arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Memory Controllers (SDRAMC only) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_SDRAMC_H
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#define AT91RM9200_SDRAMC_H
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/* SDRAM Controller registers */
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#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
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#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
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#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
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#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
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#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
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#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
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#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
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#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
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#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
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#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
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#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
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#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
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#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
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#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
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#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
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#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
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#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
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#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
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#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
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#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
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#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
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#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
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#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
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#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
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#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
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#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
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#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
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#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
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#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
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#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
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#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
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#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
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#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
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#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
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#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
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#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
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#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
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#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
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#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
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#endif