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drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/

For the shared paths on the next generation chipsets.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>

authored by Chris Wilson and committed by Eric Anholt 90eb77ba 72bcb269

+37 -37
unified split
+37 -37
drivers/gpu/drm/i915/i915_suspend.c
··· 34 34 struct drm_i915_private *dev_priv = dev->dev_private; 35 35 u32 dpll_reg; 36 36 37 - if (IS_IRONLAKE(dev)) { 37 + if (HAS_PCH_SPLIT(dev)) { 38 38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B; 39 39 } else { 40 40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B; ··· 53 53 if (!i915_pipe_enabled(dev, pipe)) 54 54 return; 55 55 56 - if (IS_IRONLAKE(dev)) 56 + if (HAS_PCH_SPLIT(dev)) 57 57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 58 58 59 59 if (pipe == PIPE_A) ··· 75 75 if (!i915_pipe_enabled(dev, pipe)) 76 76 return; 77 77 78 - if (IS_IRONLAKE(dev)) 78 + if (HAS_PCH_SPLIT(dev)) 79 79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 80 80 81 81 if (pipe == PIPE_A) ··· 239 239 if (drm_core_check_feature(dev, DRIVER_MODESET)) 240 240 return; 241 241 242 - if (IS_IRONLAKE(dev)) { 242 + if (HAS_PCH_SPLIT(dev)) { 243 243 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL); 244 244 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL); 245 245 } ··· 247 247 /* Pipe & plane A info */ 248 248 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 249 249 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 250 - if (IS_IRONLAKE(dev)) { 250 + if (HAS_PCH_SPLIT(dev)) { 251 251 dev_priv->saveFPA0 = I915_READ(PCH_FPA0); 252 252 dev_priv->saveFPA1 = I915_READ(PCH_FPA1); 253 253 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A); ··· 256 256 dev_priv->saveFPA1 = I915_READ(FPA1); 257 257 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 258 258 } 259 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 259 + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) 260 260 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 261 261 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 262 262 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); ··· 264 264 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 265 265 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 266 266 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 267 - if (!IS_IRONLAKE(dev)) 267 + if (!HAS_PCH_SPLIT(dev)) 268 268 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 269 269 270 - if (IS_IRONLAKE(dev)) { 270 + if (HAS_PCH_SPLIT(dev)) { 271 271 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1); 272 272 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1); 273 273 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1); ··· 304 304 /* Pipe & plane B info */ 305 305 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 306 306 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 307 - if (IS_IRONLAKE(dev)) { 307 + if (HAS_PCH_SPLIT(dev)) { 308 308 dev_priv->saveFPB0 = I915_READ(PCH_FPB0); 309 309 dev_priv->saveFPB1 = I915_READ(PCH_FPB1); 310 310 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B); ··· 313 313 dev_priv->saveFPB1 = I915_READ(FPB1); 314 314 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 315 315 } 316 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 316 + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) 317 317 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 318 318 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 319 319 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); ··· 321 321 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 322 322 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 323 323 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 324 - if (!IS_IRONLAKE(dev)) 324 + if (!HAS_PCH_SPLIT(dev)) 325 325 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B); 326 326 327 - if (IS_IRONLAKE(dev)) { 327 + if (HAS_PCH_SPLIT(dev)) { 328 328 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1); 329 329 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1); 330 330 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1); ··· 369 369 if (drm_core_check_feature(dev, DRIVER_MODESET)) 370 370 return; 371 371 372 - if (IS_IRONLAKE(dev)) { 372 + if (HAS_PCH_SPLIT(dev)) { 373 373 dpll_a_reg = PCH_DPLL_A; 374 374 dpll_b_reg = PCH_DPLL_B; 375 375 fpa0_reg = PCH_FPA0; ··· 385 385 fpb1_reg = FPB1; 386 386 } 387 387 388 - if (IS_IRONLAKE(dev)) { 388 + if (HAS_PCH_SPLIT(dev)) { 389 389 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL); 390 390 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL); 391 391 } ··· 404 404 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); 405 405 POSTING_READ(dpll_a_reg); 406 406 udelay(150); 407 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) { 407 + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { 408 408 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 409 409 POSTING_READ(DPLL_A_MD); 410 410 } ··· 417 417 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 418 418 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 419 419 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 420 - if (!IS_IRONLAKE(dev)) 420 + if (!HAS_PCH_SPLIT(dev)) 421 421 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 422 422 423 - if (IS_IRONLAKE(dev)) { 423 + if (HAS_PCH_SPLIT(dev)) { 424 424 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1); 425 425 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1); 426 426 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1); ··· 473 473 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B); 474 474 POSTING_READ(dpll_b_reg); 475 475 udelay(150); 476 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) { 476 + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { 477 477 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 478 478 POSTING_READ(DPLL_B_MD); 479 479 } ··· 486 486 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 487 487 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 488 488 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 489 - if (!IS_IRONLAKE(dev)) 489 + if (!HAS_PCH_SPLIT(dev)) 490 490 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 491 491 492 - if (IS_IRONLAKE(dev)) { 492 + if (HAS_PCH_SPLIT(dev)) { 493 493 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1); 494 494 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1); 495 495 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1); ··· 554 554 dev_priv->saveCURSIZE = I915_READ(CURSIZE); 555 555 556 556 /* CRT state */ 557 - if (IS_IRONLAKE(dev)) { 557 + if (HAS_PCH_SPLIT(dev)) { 558 558 dev_priv->saveADPA = I915_READ(PCH_ADPA); 559 559 } else { 560 560 dev_priv->saveADPA = I915_READ(ADPA); 561 561 } 562 562 563 563 /* LVDS state */ 564 - if (IS_IRONLAKE(dev)) { 564 + if (HAS_PCH_SPLIT(dev)) { 565 565 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL); 566 566 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); 567 567 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); ··· 579 579 dev_priv->saveLVDS = I915_READ(LVDS); 580 580 } 581 581 582 - if (!IS_I830(dev) && !IS_845G(dev) && !IS_IRONLAKE(dev)) 582 + if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) 583 583 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 584 584 585 - if (IS_IRONLAKE(dev)) { 585 + if (HAS_PCH_SPLIT(dev)) { 586 586 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); 587 587 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); 588 588 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); ··· 610 610 611 611 /* Only save FBC state on the platform that supports FBC */ 612 612 if (I915_HAS_FBC(dev)) { 613 - if (IS_IRONLAKE_M(dev)) { 613 + if (HAS_PCH_SPLIT(dev)) { 614 614 dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE); 615 615 } else if (IS_GM45(dev)) { 616 616 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE); ··· 626 626 dev_priv->saveVGA0 = I915_READ(VGA0); 627 627 dev_priv->saveVGA1 = I915_READ(VGA1); 628 628 dev_priv->saveVGA_PD = I915_READ(VGA_PD); 629 - if (IS_IRONLAKE(dev)) 629 + if (HAS_PCH_SPLIT(dev)) 630 630 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL); 631 631 else 632 632 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); ··· 668 668 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); 669 669 670 670 /* CRT state */ 671 - if (IS_IRONLAKE(dev)) 671 + if (HAS_PCH_SPLIT(dev)) 672 672 I915_WRITE(PCH_ADPA, dev_priv->saveADPA); 673 673 else 674 674 I915_WRITE(ADPA, dev_priv->saveADPA); 675 675 676 676 /* LVDS state */ 677 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 677 + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) 678 678 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 679 679 680 - if (IS_IRONLAKE(dev)) { 680 + if (HAS_PCH_SPLIT(dev)) { 681 681 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS); 682 682 } else if (IS_MOBILE(dev) && !IS_I830(dev)) 683 683 I915_WRITE(LVDS, dev_priv->saveLVDS); 684 684 685 - if (!IS_I830(dev) && !IS_845G(dev) && !IS_IRONLAKE(dev)) 685 + if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) 686 686 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); 687 687 688 - if (IS_IRONLAKE(dev)) { 688 + if (HAS_PCH_SPLIT(dev)) { 689 689 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); 690 690 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); 691 691 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); ··· 716 716 717 717 /* only restore FBC info on the platform that supports FBC*/ 718 718 if (I915_HAS_FBC(dev)) { 719 - if (IS_IRONLAKE_M(dev)) { 719 + if (HAS_PCH_SPLIT(dev)) { 720 720 ironlake_disable_fbc(dev); 721 721 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE); 722 722 } else if (IS_GM45(dev)) { ··· 731 731 } 732 732 } 733 733 /* VGA state */ 734 - if (IS_IRONLAKE(dev)) 734 + if (HAS_PCH_SPLIT(dev)) 735 735 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); 736 736 else 737 737 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); ··· 757 757 i915_save_display(dev); 758 758 759 759 /* Interrupt state */ 760 - if (IS_IRONLAKE(dev)) { 760 + if (HAS_PCH_SPLIT(dev)) { 761 761 dev_priv->saveDEIER = I915_READ(DEIER); 762 762 dev_priv->saveDEIMR = I915_READ(DEIMR); 763 763 dev_priv->saveGTIER = I915_READ(GTIER); ··· 771 771 dev_priv->saveIMR = I915_READ(IMR); 772 772 } 773 773 774 - if (IS_IRONLAKE_M(dev)) 774 + if (HAS_PCH_SPLIT(dev)) 775 775 ironlake_disable_drps(dev); 776 776 777 777 /* Cache mode state */ ··· 829 829 i915_restore_display(dev); 830 830 831 831 /* Interrupt state */ 832 - if (IS_IRONLAKE(dev)) { 832 + if (HAS_PCH_SPLIT(dev)) { 833 833 I915_WRITE(DEIER, dev_priv->saveDEIER); 834 834 I915_WRITE(DEIMR, dev_priv->saveDEIMR); 835 835 I915_WRITE(GTIER, dev_priv->saveGTIER); ··· 844 844 /* Clock gating state */ 845 845 intel_init_clock_gating(dev); 846 846 847 - if (IS_IRONLAKE_M(dev)) 847 + if (HAS_PCH_SPLIT(dev)) 848 848 ironlake_enable_drps(dev); 849 849 850 850 /* Cache mode state */