tjh.dev / kernel
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drm/i915/suspend: Flush register writes before busy-waiting.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>

authored by Chris Wilson and committed by Eric Anholt 72bcb269 d5dd96cb

+18 -9
unified split
+18 -9
drivers/gpu/drm/i915/i915_suspend.c
··· 395 395 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 396 396 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A & 397 397 ~DPLL_VCO_ENABLE); 398 - DRM_UDELAY(150); 398 + POSTING_READ(dpll_a_reg); 399 + udelay(150); 399 400 } 400 401 I915_WRITE(fpa0_reg, dev_priv->saveFPA0); 401 402 I915_WRITE(fpa1_reg, dev_priv->saveFPA1); 402 403 /* Actually enable it */ 403 404 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); 404 - DRM_UDELAY(150); 405 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 405 + POSTING_READ(dpll_a_reg); 406 + udelay(150); 407 + if (IS_I965G(dev) && !IS_IRONLAKE(dev)) { 406 408 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 407 - DRM_UDELAY(150); 409 + POSTING_READ(DPLL_A_MD); 410 + } 411 + udelay(150); 408 412 409 413 /* Restore mode */ 410 414 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); ··· 464 460 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 465 461 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B & 466 462 ~DPLL_VCO_ENABLE); 467 - DRM_UDELAY(150); 463 + POSTING_READ(dpll_b_reg); 464 + udelay(150); 468 465 } 469 466 I915_WRITE(fpb0_reg, dev_priv->saveFPB0); 470 467 I915_WRITE(fpb1_reg, dev_priv->saveFPB1); 471 468 /* Actually enable it */ 472 469 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B); 473 - DRM_UDELAY(150); 474 - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 470 + POSTING_READ(dpll_b_reg); 471 + udelay(150); 472 + if (IS_I965G(dev) && !IS_IRONLAKE(dev)) { 475 473 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 476 - DRM_UDELAY(150); 474 + POSTING_READ(DPLL_B_MD); 475 + } 476 + udelay(150); 477 477 478 478 /* Restore mode */ 479 479 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); ··· 738 730 I915_WRITE(VGA0, dev_priv->saveVGA0); 739 731 I915_WRITE(VGA1, dev_priv->saveVGA1); 740 732 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 741 - DRM_UDELAY(150); 733 + POSTING_READ(VGA_PD); 734 + udelay(150); 742 735 743 736 i915_restore_vga(dev); 744 737 }