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Merge tag 'drm/tegra/for-3.20-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-fixes

drm/tegra: Fixes for v3.20-rc1

This fixes a bit of fallout that was caused by the atomic modesetting
driver conversion and some last-minute changes in the DRM atomic core.
It also fixes a bug exposed by recent changes in the clock framework
which results in non-working HDMI.

* tag 'drm/tegra/for-3.20-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux:
drm/tegra: dc: Move more code into ->init()
drm/tegra: dc: Wire up CRTC parent of atomic state
drm/tegra: dc: Reset state's active_changed field
drm/tegra: hdmi: Explicitly set clock rate

Dave Airlie 8ee35162 2caa80e7

+48 -39
+40 -39
drivers/gpu/drm/tegra/dc.c
··· 997 997 crtc->state = NULL; 998 998 999 999 state = kzalloc(sizeof(*state), GFP_KERNEL); 1000 - if (state) 1000 + if (state) { 1001 1001 crtc->state = &state->base; 1002 + crtc->state->crtc = crtc; 1003 + } 1002 1004 } 1003 1005 1004 1006 static struct drm_crtc_state * ··· 1014 1012 return NULL; 1015 1013 1016 1014 copy->base.mode_changed = false; 1015 + copy->base.active_changed = false; 1017 1016 copy->base.planes_changed = false; 1018 1017 copy->base.event = NULL; 1019 1018 ··· 1230 1227 /* program display mode */ 1231 1228 tegra_dc_set_timings(dc, mode); 1232 1229 1233 - if (dc->soc->supports_border_color) 1234 - tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 1235 - 1236 1230 /* interlacing isn't supported yet, so disable it */ 1237 1231 if (dc->soc->supports_interlacing) { 1238 1232 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); ··· 1252 1252 1253 1253 static void tegra_crtc_prepare(struct drm_crtc *crtc) 1254 1254 { 1255 - struct tegra_dc *dc = to_tegra_dc(crtc); 1256 - unsigned int syncpt; 1257 - unsigned long value; 1258 - 1259 1255 drm_crtc_vblank_off(crtc); 1260 - 1261 - if (dc->pipe) 1262 - syncpt = SYNCPT_VBLANK1; 1263 - else 1264 - syncpt = SYNCPT_VBLANK0; 1265 - 1266 - /* initialize display controller */ 1267 - tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 1268 - tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); 1269 - 1270 - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; 1271 - tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1272 - 1273 - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1274 - WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1275 - tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 1276 - 1277 - /* initialize timer */ 1278 - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 1279 - WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 1280 - tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 1281 - 1282 - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 1283 - WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 1284 - tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 1285 - 1286 - value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 1287 - tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 1288 - 1289 - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 1290 - tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1291 1256 } 1292 1257 1293 1258 static void tegra_crtc_commit(struct drm_crtc *crtc) ··· 1629 1664 struct tegra_drm *tegra = drm->dev_private; 1630 1665 struct drm_plane *primary = NULL; 1631 1666 struct drm_plane *cursor = NULL; 1667 + unsigned int syncpt; 1668 + u32 value; 1632 1669 int err; 1633 1670 1634 1671 if (tegra->domain) { ··· 1696 1729 err); 1697 1730 goto cleanup; 1698 1731 } 1732 + 1733 + /* initialize display controller */ 1734 + if (dc->pipe) 1735 + syncpt = SYNCPT_VBLANK1; 1736 + else 1737 + syncpt = SYNCPT_VBLANK0; 1738 + 1739 + tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 1740 + tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); 1741 + 1742 + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; 1743 + tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1744 + 1745 + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1746 + WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1747 + tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 1748 + 1749 + /* initialize timer */ 1750 + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 1751 + WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 1752 + tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 1753 + 1754 + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 1755 + WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 1756 + tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 1757 + 1758 + value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 1759 + tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 1760 + 1761 + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 1762 + tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1763 + 1764 + if (dc->soc->supports_border_color) 1765 + tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 1699 1766 1700 1767 return 0; 1701 1768
+8
drivers/gpu/drm/tegra/hdmi.c
··· 851 851 h_back_porch = mode->htotal - mode->hsync_end; 852 852 h_front_porch = mode->hsync_start - mode->hdisplay; 853 853 854 + err = clk_set_rate(hdmi->clk, pclk); 855 + if (err < 0) { 856 + dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n", 857 + err); 858 + } 859 + 860 + DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk)); 861 + 854 862 /* power up sequence */ 855 863 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); 856 864 value &= ~SOR_PLL_PDBG;