[PATCH] ARM: Add V6 aliasing cache flush

Add cache flushing support for aliased V6 caches to
flush_dcache_page.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>

+35 -2
+35 -2
arch/arm/mm/flush.c
··· 13 14 #include <asm/cacheflush.h> 15 #include <asm/system.h> 16 17 static void __flush_dcache_page(struct address_space *mapping, struct page *page) 18 { ··· 60 return; 61 62 /* 63 * There are possible user space mappings of this page: 64 * - VIVT cache: we need to also write back and invalidate all user 65 * data in the current VM view associated with this page. ··· 92 continue; 93 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; 94 flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page)); 95 - if (cache_is_vipt()) 96 - break; 97 } 98 flush_dcache_mmap_unlock(mapping); 99 }
··· 13 14 #include <asm/cacheflush.h> 15 #include <asm/system.h> 16 + #include <asm/tlbflush.h> 17 + 18 + #ifdef CONFIG_CPU_CACHE_VIPT 19 + #define ALIAS_FLUSH_START 0xffff4000 20 + 21 + #define TOP_PTE(x) pte_offset_kernel(top_pmd, x) 22 + 23 + static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) 24 + { 25 + unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); 26 + 27 + set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); 28 + flush_tlb_kernel_page(to); 29 + 30 + asm( "mcrr p15, 0, %1, %0, c14\n" 31 + " mcrr p15, 0, %1, %0, c5\n" 32 + : 33 + : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES) 34 + : "cc"); 35 + } 36 + #else 37 + #define flush_pfn_alias(pfn,vaddr) do { } while (0) 38 + #endif 39 40 static void __flush_dcache_page(struct address_space *mapping, struct page *page) 41 { ··· 37 return; 38 39 /* 40 + * This is a page cache page. If we have a VIPT cache, we 41 + * only need to do one flush - which would be at the relevant 42 + * userspace colour, which is congruent with page->index. 43 + */ 44 + if (cache_is_vipt()) { 45 + if (cache_is_vipt_aliasing()) 46 + flush_pfn_alias(page_to_pfn(page), 47 + page->index << PAGE_CACHE_SHIFT); 48 + return; 49 + } 50 + 51 + /* 52 * There are possible user space mappings of this page: 53 * - VIVT cache: we need to also write back and invalidate all user 54 * data in the current VM view associated with this page. ··· 57 continue; 58 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; 59 flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page)); 60 } 61 flush_dcache_mmap_unlock(mapping); 62 }