Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
[PATCH] ARM: Add V6 aliasing cache flush
Add cache flushing support for aliased V6 caches to
flush_dcache_page.
Signed-off-by: Russell King <rmk@arm.linux.org.uk>
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-2
arch/arm/mm/flush.c
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arch/arm/mm/flush.c
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#include <asm/cacheflush.h>
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#include <asm/system.h>
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#include <asm/tlbflush.h>
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#ifdef CONFIG_CPU_CACHE_VIPT
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#define ALIAS_FLUSH_START 0xffff4000
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#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
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static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
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{
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unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
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set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL));
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flush_tlb_kernel_page(to);
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asm( "mcrr p15, 0, %1, %0, c14\n"
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" mcrr p15, 0, %1, %0, c5\n"
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:
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: "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES)
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: "cc");
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}
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#else
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#define flush_pfn_alias(pfn,vaddr) do { } while (0)
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#endif
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static void __flush_dcache_page(struct address_space *mapping, struct page *page)
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{
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return;
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/*
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* This is a page cache page. If we have a VIPT cache, we
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* only need to do one flush - which would be at the relevant
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* userspace colour, which is congruent with page->index.
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*/
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if (cache_is_vipt()) {
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if (cache_is_vipt_aliasing())
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flush_pfn_alias(page_to_pfn(page),
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page->index << PAGE_CACHE_SHIFT);
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return;
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}
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/*
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* There are possible user space mappings of this page:
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* - VIVT cache: we need to also write back and invalidate all user
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* data in the current VM view associated with this page.
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continue;
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offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
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flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page));
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if (cache_is_vipt())
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break;
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}
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flush_dcache_mmap_unlock(mapping);
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}