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linux
drm/amd/powerplay: update vega20 clocks threshold settings on power state adjust
UVD, VCE and SOC clocks need to be taken into consideration. Also, the
thresholds need be updated correspondingly when stable power state is selected.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Evan Quan
and committed by
Alex Deucher
8c191fe3
acd11624
+112
+112
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+112
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
···
2503
2503
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2504
2504
dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2505
2505
2506
+
if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2507
+
if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2508
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2509
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2510
+
}
2511
+
2512
+
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2513
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2514
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2515
+
}
2516
+
2517
+
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2518
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2519
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2520
+
}
2521
+
}
2522
+
2506
2523
/* memclk */
2507
2524
dpm_table = &(data->dpm_table.mem_table);
2508
2525
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
···
2527
2510
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2528
2511
dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2529
2512
2513
+
if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2514
+
if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2515
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2516
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2517
+
}
2518
+
2519
+
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2520
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2521
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2522
+
}
2523
+
2524
+
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2525
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2526
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2527
+
}
2528
+
}
2529
+
2530
+
/* honour DAL's UCLK Hardmin */
2530
2531
if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
2531
2532
dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
2532
2533
2534
+
/* Hardmin is dependent on displayconfig */
2533
2535
if (disable_mclk_switching) {
2534
2536
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2535
2537
for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
···
2563
2527
2564
2528
if (hwmgr->display_config->nb_pstate_switch_disable)
2565
2529
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2530
+
2531
+
/* vclk */
2532
+
dpm_table = &(data->dpm_table.vclk_table);
2533
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2534
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2535
+
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2536
+
dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2537
+
2538
+
if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2539
+
if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2540
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2541
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2542
+
}
2543
+
2544
+
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2545
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2546
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2547
+
}
2548
+
}
2549
+
2550
+
/* dclk */
2551
+
dpm_table = &(data->dpm_table.dclk_table);
2552
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2553
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2554
+
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2555
+
dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2556
+
2557
+
if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2558
+
if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2559
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2560
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2561
+
}
2562
+
2563
+
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2564
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2565
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2566
+
}
2567
+
}
2568
+
2569
+
/* socclk */
2570
+
dpm_table = &(data->dpm_table.soc_table);
2571
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2572
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2573
+
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2574
+
dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2575
+
2576
+
if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2577
+
if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2578
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2579
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2580
+
}
2581
+
2582
+
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2583
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2584
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2585
+
}
2586
+
}
2587
+
2588
+
/* eclk */
2589
+
dpm_table = &(data->dpm_table.eclk_table);
2590
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2591
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2592
+
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2593
+
dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2594
+
2595
+
if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2596
+
if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2597
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2598
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2599
+
}
2600
+
2601
+
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2602
+
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2603
+
dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2604
+
}
2605
+
}
2566
2606
2567
2607
return 0;
2568
2608
}