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drm/amd/powerplay: revise vega20 PPSMC_MSG_SetSoftMin/[Max]ByFreq settings

UVD, VCE and Socclk also need to be taken into consideration when
setting PPSMC_MSG_SetSoftMinByFreq and PPSMC_MSG_SetSoftMaxByFreq.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Evan Quan and committed by
Alex Deucher acd11624 d617d4d7

+96 -13
+96 -13
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
··· 1485 1485 { 1486 1486 struct vega20_hwmgr *data = 1487 1487 (struct vega20_hwmgr *)(hwmgr->backend); 1488 + uint32_t min_freq; 1488 1489 int ret = 0; 1489 1490 1490 - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) 1491 + if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1492 + min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; 1491 1493 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1492 1494 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1493 - PPCLK_GFXCLK << 16 | 1494 - data->dpm_table.gfx_table.dpm_state.soft_min_level)), 1495 + (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))), 1495 1496 "Failed to set soft min gfxclk !", 1496 1497 return ret); 1498 + } 1497 1499 1498 1500 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1501 + min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; 1499 1502 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1500 1503 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1501 - PPCLK_UCLK << 16 | 1502 - data->dpm_table.mem_table.dpm_state.soft_min_level)), 1504 + (PPCLK_UCLK << 16) | (min_freq & 0xffff))), 1503 1505 "Failed to set soft min memclk !", 1504 1506 return ret); 1507 + 1508 + min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level; 1505 1509 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1506 1510 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1507 - PPCLK_UCLK << 16 | 1508 - data->dpm_table.mem_table.dpm_state.hard_min_level)), 1511 + (PPCLK_UCLK << 16) | (min_freq & 0xffff))), 1509 1512 "Failed to set hard min memclk !", 1513 + return ret); 1514 + } 1515 + 1516 + if (data->smu_features[GNLD_DPM_UVD].enabled) { 1517 + min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; 1518 + 1519 + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1520 + hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1521 + (PPCLK_VCLK << 16) | (min_freq & 0xffff))), 1522 + "Failed to set soft min vclk!", 1523 + return ret); 1524 + 1525 + min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; 1526 + 1527 + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1528 + hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1529 + (PPCLK_DCLK << 16) | (min_freq & 0xffff))), 1530 + "Failed to set soft min dclk!", 1531 + return ret); 1532 + } 1533 + 1534 + if (data->smu_features[GNLD_DPM_VCE].enabled) { 1535 + min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; 1536 + 1537 + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1538 + hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1539 + (PPCLK_ECLK << 16) | (min_freq & 0xffff))), 1540 + "Failed to set soft min eclk!", 1541 + return ret); 1542 + } 1543 + 1544 + if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1545 + min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; 1546 + 1547 + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1548 + hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1549 + (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))), 1550 + "Failed to set soft min socclk!", 1510 1551 return ret); 1511 1552 } 1512 1553 ··· 1558 1517 { 1559 1518 struct vega20_hwmgr *data = 1560 1519 (struct vega20_hwmgr *)(hwmgr->backend); 1520 + uint32_t max_freq; 1561 1521 int ret = 0; 1562 1522 1563 - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) 1523 + if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1524 + max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; 1525 + 1564 1526 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1565 1527 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1566 - PPCLK_GFXCLK << 16 | 1567 - data->dpm_table.gfx_table.dpm_state.soft_max_level)), 1528 + (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))), 1568 1529 "Failed to set soft max gfxclk!", 1569 1530 return ret); 1531 + } 1570 1532 1571 - if (data->smu_features[GNLD_DPM_UCLK].enabled) 1533 + if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1534 + max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; 1535 + 1572 1536 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1573 1537 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1574 - PPCLK_UCLK << 16 | 1575 - data->dpm_table.mem_table.dpm_state.soft_max_level)), 1538 + (PPCLK_UCLK << 16) | (max_freq & 0xffff))), 1576 1539 "Failed to set soft max memclk!", 1577 1540 return ret); 1541 + } 1542 + 1543 + if (data->smu_features[GNLD_DPM_UVD].enabled) { 1544 + max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; 1545 + 1546 + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1547 + hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1548 + (PPCLK_VCLK << 16) | (max_freq & 0xffff))), 1549 + "Failed to set soft max vclk!", 1550 + return ret); 1551 + 1552 + max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; 1553 + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1554 + hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1555 + (PPCLK_DCLK << 16) | (max_freq & 0xffff))), 1556 + "Failed to set soft max dclk!", 1557 + return ret); 1558 + } 1559 + 1560 + if (data->smu_features[GNLD_DPM_VCE].enabled) { 1561 + max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; 1562 + 1563 + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1564 + hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1565 + (PPCLK_ECLK << 16) | (max_freq & 0xffff))), 1566 + "Failed to set soft max eclk!", 1567 + return ret); 1568 + } 1569 + 1570 + if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1571 + max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; 1572 + 1573 + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1574 + hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1575 + (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))), 1576 + "Failed to set soft max socclk!", 1577 + return ret); 1578 + } 1578 1579 1579 1580 return ret; 1580 1581 }