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kernel
os
linux
clk: st: Adds clockgen clock binding
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
authored by
Gabriel FERNANDEZ
and committed by
Mike Turquette
8b221488
be10afcd
+48
+48
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+48
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
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Binding for a ST pll clock driver.
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This binding uses the common clock binding[1].
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Base address is located to the parent node. See clock binding[2]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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Required properties:
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- compatible : shall be:
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"st,clkgena-prediv-c65", "st,clkgena-prediv"
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"st,clkgena-prediv-c32", "st,clkgena-prediv"
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"st,clkgena-plls-c65"
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"st,plls-c32-a1x-0", "st,clkgen-plls-c32"
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"st,plls-c32-a1x-1", "st,clkgen-plls-c32"
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"st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
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"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
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"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
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"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
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"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
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"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
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- #clock-cells : From common clock binding; shall be set to 1.
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- clocks : From common clock binding
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- clock-output-names : From common clock binding.
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Example:
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clockgenA@fee62000 {
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reg = <0xfee62000 0xb48>;
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CLK_S_A0_PLL: CLK_S_A0_PLL {
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#clock-cells = <1>;
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compatible = "st,clkgena-plls-c65";
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clocks = <&CLK_SYSIN>;
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clock-output-names = "CLK_S_A0_PLL0_HS",
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"CLK_S_A0_PLL0_LS",
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"CLK_S_A0_PLL1";
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};
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};