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linux
clk: st: Adds divmux and prediv clock binding
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
authored by
Gabriel FERNANDEZ
and committed by
Mike Turquette
be10afcd
ab35dc13
+168
+49
Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
+49
Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
···
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Binding for a ST divider and multiplexer clock driver.
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This binding uses the common clock binding[1].
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Base address is located to the parent node. See clock binding[2]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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Required properties:
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- compatible : shall be:
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"st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
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"st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
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"st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
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"st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
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"st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
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"st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"
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- #clock-cells : From common clock binding; shall be set to 1.
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- clocks : From common clock binding
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- clock-output-names : From common clock binding.
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Example:
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clockgenA@fd345000 {
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reg = <0xfd345000 0xb50>;
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CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf1",
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"st,clkgena-divmux";
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clocks = <&CLK_M_A1_OSC_PREDIV>,
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<&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
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<&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
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clock-output-names = "CLK_M_RX_ICN_TS",
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"CLK_M_RX_ICN_VDP_0",
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"", /* Unused */
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"CLK_M_PRV_T1_BUS",
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"CLK_M_ICN_REG_12",
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"CLK_M_ICN_REG_10",
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"", /* Unused */
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"CLK_M_ICN_ST231";
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};
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};
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+36
Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
+36
Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
···
1
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Binding for a ST pre-divider clock driver.
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3
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This binding uses the common clock binding[1].
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Base address is located to the parent node. See clock binding[2]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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Required properties:
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- compatible : shall be:
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"st,clkgena-prediv-c65", "st,clkgena-prediv"
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"st,clkgena-prediv-c32", "st,clkgena-prediv"
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- #clock-cells : From common clock binding; shall be set to 0.
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- clocks : From common clock binding
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- clock-output-names : From common clock binding.
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Example:
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clockgenA@fd345000 {
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reg = <0xfd345000 0xb50>;
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CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c32",
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"st,clkgena-prediv";
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clocks = <&CLK_SYSIN>;
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clock-output-names = "CLK_M_A2_OSC_PREDIV";
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};
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};
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+83
Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+83
Documentation/devicetree/bindings/clock/st/st,clkgen.txt
···
1
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Binding for a Clockgen hardware block found on
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certain STMicroelectronics consumer electronics SoC devices.
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A Clockgen node can contain pll, diviser or multiplexer nodes.
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We will find only the base address of the Clockgen, this base
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address is common of all subnode.
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clockgen_node {
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reg = <>;
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pll_node {
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...
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};
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prediv_node {
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...
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};
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divmux_node {
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...
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};
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quadfs_node {
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...
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};
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...
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};
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This binding uses the common clock binding[1].
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Each subnode should use the binding discribe in [2]..[4]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
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[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
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[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
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Required properties:
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- reg : A Base address and length of the register set.
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Example:
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clockgenA@fee62000 {
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reg = <0xfee62000 0xb48>;
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CLK_S_A0_PLL: CLK_S_A0_PLL {
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#clock-cells = <1>;
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compatible = "st,clkgena-plls-c65";
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clocks = <&CLK_SYSIN>;
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clock-output-names = "CLK_S_A0_PLL0_HS",
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"CLK_S_A0_PLL0_LS",
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"CLK_S_A0_PLL1";
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};
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CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c65",
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"st,clkgena-prediv";
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clocks = <&CLK_SYSIN>;
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clock-output-names = "CLK_S_A0_OSC_PREDIV";
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};
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CLK_S_A0_HS: CLK_S_A0_HS {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-hs",
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"st,clkgena-divmux";
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clocks = <&CLK_S_A0_OSC_PREDIV>,
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<&CLK_S_A0_PLL 0>, /* PLL0 HS */
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<&CLK_S_A0_PLL 2>; /* PLL1 */
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clock-output-names = "CLK_S_FDMA_0",
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"CLK_S_FDMA_1",
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""; /* CLK_S_JIT_SENSE */
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/* Fourth output unused */
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};
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};
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