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linux
dt-bindings: clock: mediatek: add bindings for MT8167 clocks
Add binding documentation for topckgen, apmixedsys, infracfg, audsys,
imgsys, mfgcfg, vdecsys on MT8167 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200918132303.2831815-1-fparent@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Fabien Parent
and committed by
Stephen Boyd
8adea9b9
804a8924
+138
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
···
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- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
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- "mediatek,mt7629-apmixedsys"
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- "mediatek,mt8135-apmixedsys"
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- "mediatek,mt8167-apmixedsys", "syscon"
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- "mediatek,mt8173-apmixedsys"
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- "mediatek,mt8183-apmixedsys", "syscon"
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- "mediatek,mt8516-apmixedsys"
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
···
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- "mediatek,mt6779-audio", "syscon"
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- "mediatek,mt7622-audsys", "syscon"
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- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt8167-audiosys", "syscon"
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- "mediatek,mt8183-audiosys", "syscon"
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- "mediatek,mt8516-audsys", "syscon"
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- #clock-cells: Must be 1
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
···
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- "mediatek,mt6779-imgsys", "syscon"
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- "mediatek,mt6797-imgsys", "syscon"
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- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt8167-imgsys", "syscon"
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- "mediatek,mt8173-imgsys", "syscon"
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- "mediatek,mt8183-imgsys", "syscon"
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- #clock-cells: Must be 1
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
···
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- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt7629-infracfg", "syscon"
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- "mediatek,mt8135-infracfg", "syscon"
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- "mediatek,mt8167-infracfg", "syscon"
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- "mediatek,mt8173-infracfg", "syscon"
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- "mediatek,mt8183-infracfg", "syscon"
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- "mediatek,mt8516-infracfg", "syscon"
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+1
Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
···
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- "mediatek,mt6779-vdecsys", "syscon"
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- "mediatek,mt6797-vdecsys", "syscon"
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- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt8167-vdecsys", "syscon"
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- "mediatek,mt8173-vdecsys", "syscon"
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- "mediatek,mt8183-vdecsys", "syscon"
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- #clock-cells: Must be 1
+131
include/dt-bindings/clock/mt8167-clk.h
+131
include/dt-bindings/clock/mt8167-clk.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Copyright (c) 2020 BayLibre, SAS.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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* Fabien Parent <fparent@baylibre.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT8167_H
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#define _DT_BINDINGS_CLK_MT8167_H
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/* MT8167 is based on MT8516 */
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#include <dt-bindings/clock/mt8516-clk.h>
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/* APMIXEDSYS */
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#define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0)
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#define CLK_APMIXED_LVDSPLL (CLK_APMIXED_NR_CLK + 1)
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#define CLK_APMIXED_HDMI_REF (CLK_APMIXED_NR_CLK + 2)
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#define MT8167_CLK_APMIXED_NR_CLK (CLK_APMIXED_NR_CLK + 3)
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/* TOPCKGEN */
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#define CLK_TOP_DSI0_LNTC_DSICK (CLK_TOP_NR_CLK + 0)
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#define CLK_TOP_VPLL_DPIX (CLK_TOP_NR_CLK + 1)
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#define CLK_TOP_LVDSTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 2)
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#define CLK_TOP_HDMTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 3)
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#define CLK_TOP_LVDSPLL (CLK_TOP_NR_CLK + 4)
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#define CLK_TOP_LVDSPLL_D2 (CLK_TOP_NR_CLK + 5)
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#define CLK_TOP_LVDSPLL_D4 (CLK_TOP_NR_CLK + 6)
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#define CLK_TOP_LVDSPLL_D8 (CLK_TOP_NR_CLK + 7)
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#define CLK_TOP_MIPI_26M (CLK_TOP_NR_CLK + 8)
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#define CLK_TOP_TVDPLL (CLK_TOP_NR_CLK + 9)
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#define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10)
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#define CLK_TOP_TVDPLL_D4 (CLK_TOP_NR_CLK + 11)
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#define CLK_TOP_TVDPLL_D8 (CLK_TOP_NR_CLK + 12)
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#define CLK_TOP_TVDPLL_D16 (CLK_TOP_NR_CLK + 13)
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#define CLK_TOP_PWM_MM (CLK_TOP_NR_CLK + 14)
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#define CLK_TOP_CAM_MM (CLK_TOP_NR_CLK + 15)
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#define CLK_TOP_MFG_MM (CLK_TOP_NR_CLK + 16)
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#define CLK_TOP_SPM_52M (CLK_TOP_NR_CLK + 17)
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#define CLK_TOP_MIPI_26M_DBG (CLK_TOP_NR_CLK + 18)
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#define CLK_TOP_SCAM_MM (CLK_TOP_NR_CLK + 19)
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#define CLK_TOP_SMI_MM (CLK_TOP_NR_CLK + 20)
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#define CLK_TOP_26M_HDMI_SIFM (CLK_TOP_NR_CLK + 21)
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#define CLK_TOP_26M_CEC (CLK_TOP_NR_CLK + 22)
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#define CLK_TOP_32K_CEC (CLK_TOP_NR_CLK + 23)
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#define CLK_TOP_GCPU_B (CLK_TOP_NR_CLK + 24)
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#define CLK_TOP_RG_VDEC (CLK_TOP_NR_CLK + 25)
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#define CLK_TOP_RG_FDPI0 (CLK_TOP_NR_CLK + 26)
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#define CLK_TOP_RG_FDPI1 (CLK_TOP_NR_CLK + 27)
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#define CLK_TOP_RG_AXI_MFG (CLK_TOP_NR_CLK + 28)
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#define CLK_TOP_RG_SLOW_MFG (CLK_TOP_NR_CLK + 29)
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#define CLK_TOP_GFMUX_EMI1X_SEL (CLK_TOP_NR_CLK + 30)
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#define CLK_TOP_CSW_MUX_MFG_SEL (CLK_TOP_NR_CLK + 31)
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#define CLK_TOP_CAMTG_MM_SEL (CLK_TOP_NR_CLK + 32)
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#define CLK_TOP_PWM_MM_SEL (CLK_TOP_NR_CLK + 33)
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#define CLK_TOP_SPM_52M_SEL (CLK_TOP_NR_CLK + 34)
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#define CLK_TOP_MFG_MM_SEL (CLK_TOP_NR_CLK + 35)
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#define CLK_TOP_SMI_MM_SEL (CLK_TOP_NR_CLK + 36)
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#define CLK_TOP_SCAM_MM_SEL (CLK_TOP_NR_CLK + 37)
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#define CLK_TOP_VDEC_MM_SEL (CLK_TOP_NR_CLK + 38)
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#define CLK_TOP_DPI0_MM_SEL (CLK_TOP_NR_CLK + 39)
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#define CLK_TOP_DPI1_MM_SEL (CLK_TOP_NR_CLK + 40)
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#define CLK_TOP_AXI_MFG_IN_SEL (CLK_TOP_NR_CLK + 41)
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#define CLK_TOP_SLOW_MFG_SEL (CLK_TOP_NR_CLK + 42)
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#define MT8167_CLK_TOP_NR_CLK (CLK_TOP_NR_CLK + 43)
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/* MFGCFG */
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#define CLK_MFG_BAXI 0
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#define CLK_MFG_BMEM 1
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#define CLK_MFG_BG3D 2
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#define CLK_MFG_B26M 3
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#define CLK_MFG_NR_CLK 4
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/* MMSYS */
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#define CLK_MM_SMI_COMMON 0
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#define CLK_MM_SMI_LARB0 1
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#define CLK_MM_CAM_MDP 2
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#define CLK_MM_MDP_RDMA 3
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#define CLK_MM_MDP_RSZ0 4
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#define CLK_MM_MDP_RSZ1 5
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#define CLK_MM_MDP_TDSHP 6
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#define CLK_MM_MDP_WDMA 7
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#define CLK_MM_MDP_WROT 8
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#define CLK_MM_FAKE_ENG 9
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#define CLK_MM_DISP_OVL0 10
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#define CLK_MM_DISP_RDMA0 11
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#define CLK_MM_DISP_RDMA1 12
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#define CLK_MM_DISP_WDMA 13
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#define CLK_MM_DISP_COLOR 14
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#define CLK_MM_DISP_CCORR 15
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#define CLK_MM_DISP_AAL 16
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#define CLK_MM_DISP_GAMMA 17
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#define CLK_MM_DISP_DITHER 18
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#define CLK_MM_DISP_UFOE 19
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#define CLK_MM_DISP_PWM_MM 20
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#define CLK_MM_DISP_PWM_26M 21
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#define CLK_MM_DSI_ENGINE 22
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#define CLK_MM_DSI_DIGITAL 23
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#define CLK_MM_DPI0_ENGINE 24
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#define CLK_MM_DPI0_PXL 25
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#define CLK_MM_LVDS_PXL 26
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#define CLK_MM_LVDS_CTS 27
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#define CLK_MM_DPI1_ENGINE 28
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#define CLK_MM_DPI1_PXL 29
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#define CLK_MM_HDMI_PXL 30
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#define CLK_MM_HDMI_SPDIF 31
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#define CLK_MM_HDMI_ADSP_BCK 32
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#define CLK_MM_HDMI_PLL 33
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#define CLK_MM_NR_CLK 34
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/* IMGSYS */
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#define CLK_IMG_LARB1_SMI 0
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#define CLK_IMG_CAM_SMI 1
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#define CLK_IMG_CAM_CAM 2
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#define CLK_IMG_SEN_TG 3
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#define CLK_IMG_SEN_CAM 4
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#define CLK_IMG_VENC 5
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#define CLK_IMG_NR_CLK 6
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/* VDECSYS */
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#define CLK_VDEC_CKEN 0
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#define CLK_VDEC_LARB1_CKEN 1
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#define CLK_VDEC_NR_CLK 2
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#endif /* _DT_BINDINGS_CLK_MT8167_H */