tjh.dev / kernel
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clk: mediatek: add UART0 clock support

Add MT6779 UART0 clock support.

Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Hanks Chen and committed by
Stephen Boyd 804a8924 9123e3a7

+2
+2
drivers/clk/mediatek/clk-mt6779.c
··· 919 919 "pwm_sel", 19), 920 920 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", 921 921 "pwm_sel", 21), 922 + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", 923 + "uart_sel", 22), 922 924 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", 923 925 "uart_sel", 23), 924 926 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",