tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: imx8mp-icore-mx8mp-edim2.2: correct pad settings
BIT3 and BIT0 are reserved bits, should not touch.
Fixes: aec8ad34f7f2 ("arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+20
-20
+20
-20
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts
+20
-20
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts
···
110
110
&iomuxc {
111
111
pinctrl_eqos: eqosgrp {
112
112
fsl,pins = <
113
-
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
114
-
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
115
-
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
116
-
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
117
-
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
118
-
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
119
-
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
120
-
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
121
-
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
122
-
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
123
-
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
124
-
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
125
-
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
126
-
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
127
-
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x19
113
+
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
114
+
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
115
+
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
116
+
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
117
+
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
118
+
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
119
+
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
120
+
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
121
+
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
122
+
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
123
+
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
124
+
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
125
+
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
126
+
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
127
+
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x10
128
128
>;
129
129
};
130
130
131
131
pinctrl_uart2: uart2grp {
132
132
fsl,pins = <
133
-
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
134
-
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
133
+
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
134
+
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
135
135
>;
136
136
};
137
137
···
151
151
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
152
152
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
153
153
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
154
-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
154
+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
155
155
>;
156
156
};
157
157
···
163
163
164
164
pinctrl_reg_usb1: regusb1grp {
165
165
fsl,pins = <
166
-
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
166
+
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10
167
167
>;
168
168
};
169
169
170
170
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
171
171
fsl,pins = <
172
-
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
172
+
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
173
173
>;
174
174
};
175
175
};