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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
arm64: dts: imx8mp-phyboard-pollux-rdk: correct i2c2 & mmc settings
BIT3 and BIT0 are reserved bits, should not touch.
Fixes: 88f7f6bcca37 ("arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+8
-8
+8
-8
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+8
-8
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
···
136
136
137
137
pinctrl_i2c2: i2c2grp {
138
138
fsl,pins = <
139
-
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
140
-
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
139
+
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
140
+
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
141
141
>;
142
142
};
143
143
144
144
pinctrl_i2c2_gpio: i2c2gpiogrp {
145
145
fsl,pins = <
146
-
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3
147
-
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3
146
+
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
147
+
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
148
148
>;
149
149
};
150
150
151
151
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
152
152
fsl,pins = <
153
-
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
153
+
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
154
154
>;
155
155
};
156
156
···
175
175
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
176
176
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
177
177
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
178
-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
178
+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
179
179
>;
180
180
};
181
181
···
187
187
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
188
188
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
189
189
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
190
-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
190
+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
191
191
>;
192
192
};
193
193
···
199
199
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
200
200
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
201
201
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
202
-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
202
+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
203
203
>;
204
204
};
205
205
};