tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amdgpu/vcn:Correct VCN cache window definition

Correct VCN cache window definition. The old one
is reused from UVD, and it is not fully correct.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

James Zhu and committed by
Alex Deucher 825da4d9 b17c5249

+18 -15
+1 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
··· 121 121 version_major, version_minor, family_id); 122 122 } 123 123 124 - bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE 125 - + AMDGPU_VCN_SESSION_SIZE * 40; 124 + bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; 126 125 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 127 126 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 128 127 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
+3 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
··· 24 24 #ifndef __AMDGPU_VCN_H__ 25 25 #define __AMDGPU_VCN_H__ 26 26 27 - #define AMDGPU_VCN_STACK_SIZE (200*1024) 28 - #define AMDGPU_VCN_HEAP_SIZE (256*1024) 29 - #define AMDGPU_VCN_SESSION_SIZE (50*1024) 27 + #define AMDGPU_VCN_STACK_SIZE (128*1024) 28 + #define AMDGPU_VCN_CONTEXT_SIZE (512*1024) 29 + 30 30 #define AMDGPU_VCN_FIRMWARE_OFFSET 256 31 31 #define AMDGPU_VCN_MAX_ENC_RINGS 3 32 32
+14 -10
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
··· 278 278 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 279 279 uint32_t offset; 280 280 281 + /* cache window 0: fw */ 281 282 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 282 283 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 283 284 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); ··· 298 297 299 298 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 300 299 300 + /* cache window 1: stack */ 301 301 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 302 302 lower_32_bits(adev->vcn.gpu_addr + offset)); 303 303 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 304 304 upper_32_bits(adev->vcn.gpu_addr + offset)); 305 305 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 306 - WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE); 306 + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 307 307 308 + /* cache window 2: context */ 308 309 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 309 - lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); 310 + lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 310 311 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 311 - upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); 312 + upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 312 313 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 313 - WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, 314 - AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40)); 314 + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 315 315 316 316 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 317 317 adev->gfx.config.gb_addr_config); ··· 327 325 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 328 326 uint32_t offset; 329 327 328 + /* cache window 0: fw */ 330 329 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 331 330 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 332 331 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), ··· 350 347 351 348 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 352 349 350 + /* cache window 1: stack */ 353 351 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 354 352 lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); 355 353 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 356 354 upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); 357 355 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 358 356 0xFFFFFFFF, 0); 359 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE, 357 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 360 358 0xFFFFFFFF, 0); 361 359 360 + /* cache window 2: context */ 362 361 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 363 - lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE), 362 + lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 364 363 0xFFFFFFFF, 0); 365 364 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 366 - upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE), 365 + upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 367 366 0xFFFFFFFF, 0); 368 367 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 369 - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, 370 - AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40), 368 + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 371 369 0xFFFFFFFF, 0); 372 370 373 371 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,