tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu/vcn:Replace value with defined macro

Replace value with defined macro to make
code more readable

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

James Zhu and committed by
Alex Deucher b17c5249 2dc4aa52

+18 -12
+7 -4
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
··· 309 309 /* Restore */ 310 310 ring = &adev->vcn.ring_jpeg; 311 311 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 312 - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000001L | 0x00000002L); 312 + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 313 + UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 314 + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 313 315 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 314 - lower_32_bits(ring->gpu_addr)); 316 + lower_32_bits(ring->gpu_addr)); 315 317 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 316 - upper_32_bits(ring->gpu_addr)); 318 + upper_32_bits(ring->gpu_addr)); 317 319 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 318 320 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 319 - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 321 + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 322 + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 320 323 321 324 ring = &adev->vcn.ring_dec; 322 325 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
+11 -8
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
··· 810 810 811 811 for (j = 0; j < 100; ++j) { 812 812 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 813 - if (status & 2) 813 + if (status & UVD_STATUS__IDLE) 814 814 break; 815 815 mdelay(10); 816 816 } 817 817 r = 0; 818 - if (status & 2) 818 + if (status & UVD_STATUS__IDLE) 819 819 break; 820 820 821 821 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); ··· 898 898 899 899 ring = &adev->vcn.ring_jpeg; 900 900 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 901 - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 901 + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 902 + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 902 903 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); 903 904 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); 904 905 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0); 905 906 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0); 906 - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 907 + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 907 908 908 909 /* initialize wptr */ 909 910 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); ··· 1123 1122 { 1124 1123 int ret_code; 1125 1124 1126 - /* Wait for power status to be 1 */ 1127 - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, 1125 + /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1126 + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1127 + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1128 1128 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1129 1129 1130 1130 /* disable dynamic power gating mode */ ··· 1151 1149 { 1152 1150 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1153 1151 1154 - return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2); 1152 + return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1155 1153 } 1156 1154 1157 1155 static int vcn_v1_0_wait_for_idle(void *handle) ··· 1159 1157 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1160 1158 int ret = 0; 1161 1159 1162 - SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, 0x2, 0x2, ret); 1160 + SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1161 + UVD_STATUS__IDLE, ret); 1163 1162 1164 1163 return ret; 1165 1164 }