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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};
makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.
Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
from the meson_aoclk_data struct to finally get rid on the
NR_CLKS define.
[jbrunet: Fixed whitespace checkpatch warning]
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-3-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
authored by
Neil Armstrong
and committed by
Jerome Brunet
7e1723fd
141fbc27
+68
-73
+1
drivers/clk/meson/Kconfig
+1
drivers/clk/meson/Kconfig
+22
-22
drivers/clk/meson/axg-aoclk.c
+22
-22
drivers/clk/meson/axg-aoclk.c
···
288
288
&axg_aoclk_saradc_gate,
289
289
};
290
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291
-
static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
292
-
.hws = {
293
-
[CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
294
-
[CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
295
-
[CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
296
-
[CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
297
-
[CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
298
-
[CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
299
-
[CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
300
-
[CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
301
-
[CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
302
-
[CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
303
-
[CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
304
-
[CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
305
-
[CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
306
-
[CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
307
-
[CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
308
-
[CLKID_AO_32K] = &axg_aoclk_32k.hw,
309
-
[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
310
-
},
311
-
.num = NR_CLKS,
291
+
static struct clk_hw *axg_aoclk_hw_clks[] = {
292
+
[CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
293
+
[CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
294
+
[CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
295
+
[CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
296
+
[CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
297
+
[CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
298
+
[CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
299
+
[CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
300
+
[CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
301
+
[CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
302
+
[CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
303
+
[CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
304
+
[CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
305
+
[CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
306
+
[CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
307
+
[CLKID_AO_32K] = &axg_aoclk_32k.hw,
308
+
[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
312
309
};
313
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static const struct meson_aoclk_data axg_aoclkc_data = {
···
314
317
.reset = axg_aoclk_reset,
315
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.num_clks = ARRAY_SIZE(axg_aoclk_regmap),
316
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.clks = axg_aoclk_regmap,
317
-
.hw_data = &axg_aoclk_onecell_data,
320
+
.hw_clks = {
321
+
.hws = axg_aoclk_hw_clks,
322
+
.num = ARRAY_SIZE(axg_aoclk_hw_clks),
323
+
},
318
324
};
319
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static const struct of_device_id axg_aoclkc_match_table[] = {
-2
drivers/clk/meson/axg-aoclk.h
-2
drivers/clk/meson/axg-aoclk.h
+34
-34
drivers/clk/meson/g12a-aoclk.c
+34
-34
drivers/clk/meson/g12a-aoclk.c
···
411
411
&g12a_aoclk_saradc_gate,
412
412
};
413
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414
-
static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
415
-
.hws = {
416
-
[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
417
-
[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
418
-
[CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
419
-
[CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
420
-
[CLKID_AO_UART] = &g12a_aoclk_uart.hw,
421
-
[CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
422
-
[CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
423
-
[CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
424
-
[CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
425
-
[CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
426
-
[CLKID_AO_M3] = &g12a_aoclk_m3.hw,
427
-
[CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
428
-
[CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
429
-
[CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
430
-
[CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
431
-
[CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
432
-
[CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
433
-
[CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
434
-
[CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
435
-
[CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
436
-
[CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
437
-
[CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
438
-
[CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
439
-
[CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
440
-
[CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
441
-
[CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
442
-
[CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
443
-
[CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
444
-
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
445
-
},
446
-
.num = NR_CLKS,
414
+
static struct clk_hw *g12a_aoclk_hw_clks[] = {
415
+
[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
416
+
[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
417
+
[CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
418
+
[CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
419
+
[CLKID_AO_UART] = &g12a_aoclk_uart.hw,
420
+
[CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
421
+
[CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
422
+
[CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
423
+
[CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
424
+
[CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
425
+
[CLKID_AO_M3] = &g12a_aoclk_m3.hw,
426
+
[CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
427
+
[CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
428
+
[CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
429
+
[CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
430
+
[CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
431
+
[CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
432
+
[CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
433
+
[CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
434
+
[CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
435
+
[CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
436
+
[CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
437
+
[CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
438
+
[CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
439
+
[CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
440
+
[CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
441
+
[CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
442
+
[CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
443
+
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
447
444
};
448
445
449
446
static const struct meson_aoclk_data g12a_aoclkc_data = {
···
449
452
.reset = g12a_aoclk_reset,
450
453
.num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
451
454
.clks = g12a_aoclk_regmap,
452
-
.hw_data = &g12a_aoclk_onecell_data,
455
+
.hw_clks = {
456
+
.hws = g12a_aoclk_hw_clks,
457
+
.num = ARRAY_SIZE(g12a_aoclk_hw_clks),
458
+
},
453
459
};
454
460
455
461
static const struct of_device_id g12a_aoclkc_match_table[] = {
-2
drivers/clk/meson/g12a-aoclk.h
-2
drivers/clk/meson/g12a-aoclk.h
+5
-5
drivers/clk/meson/gxbb-aoclk.c
+5
-5
drivers/clk/meson/gxbb-aoclk.c
···
252
252
&ao_cts_cec,
253
253
};
254
254
255
-
static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
256
-
.hws = {
255
+
static struct clk_hw *gxbb_aoclk_hw_clks[] = {
257
256
[CLKID_AO_REMOTE] = &remote_ao.hw,
258
257
[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
259
258
[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
···
267
268
[CLKID_AO_32K] = &ao_32k.hw,
268
269
[CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
269
270
[CLKID_AO_CLK81] = &ao_clk81.hw,
270
-
},
271
-
.num = NR_CLKS,
272
271
};
273
272
274
273
static const struct meson_aoclk_data gxbb_aoclkc_data = {
···
275
278
.reset = gxbb_aoclk_reset,
276
279
.num_clks = ARRAY_SIZE(gxbb_aoclk),
277
280
.clks = gxbb_aoclk,
278
-
.hw_data = &gxbb_aoclk_onecell_data,
281
+
.hw_clks = {
282
+
.hws = gxbb_aoclk_hw_clks,
283
+
.num = ARRAY_SIZE(gxbb_aoclk_hw_clks),
284
+
},
279
285
};
280
286
281
287
static const struct of_device_id gxbb_aoclkc_match_table[] = {
-2
drivers/clk/meson/gxbb-aoclk.h
-2
drivers/clk/meson/gxbb-aoclk.h
+4
-5
drivers/clk/meson/meson-aoclk.c
+4
-5
drivers/clk/meson/meson-aoclk.c
···
75
75
data->clks[clkid]->map = regmap;
76
76
77
77
/* Register all clks */
78
-
for (clkid = 0; clkid < data->hw_data->num; clkid++) {
79
-
if (!data->hw_data->hws[clkid])
78
+
for (clkid = 0; clkid < data->hw_clks.num; clkid++) {
79
+
if (!data->hw_clks.hws[clkid])
80
80
continue;
81
81
82
-
ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
82
+
ret = devm_clk_hw_register(dev, data->hw_clks.hws[clkid]);
83
83
if (ret) {
84
84
dev_err(dev, "Clock registration failed\n");
85
85
return ret;
86
86
}
87
87
}
88
88
89
-
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
90
-
(void *) data->hw_data);
89
+
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
91
90
}
92
91
EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
93
92
MODULE_LICENSE("GPL v2");
+2
-1
drivers/clk/meson/meson-aoclk.h
+2
-1
drivers/clk/meson/meson-aoclk.h
···
17
17
#include <linux/reset-controller.h>
18
18
19
19
#include "clk-regmap.h"
20
+
#include "meson-clkc-utils.h"
20
21
21
22
struct meson_aoclk_data {
22
23
const unsigned int reset_reg;
···
25
24
const unsigned int *reset;
26
25
const int num_clks;
27
26
struct clk_regmap **clks;
28
-
const struct clk_hw_onecell_data *hw_data;
27
+
struct meson_clk_hw_data hw_clks;
29
28
};
30
29
31
30
struct meson_aoclk_reset_controller {