tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
from the meson_eeclkc_data struct to finally get rid on the
NR_CLKS define.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-2-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

authored by

Neil Armstrong and committed by
Jerome Brunet 141fbc27 230b6f3a

+1306 -1317
+1
drivers/clk/meson/Kconfig
··· 41 41 config COMMON_CLK_MESON_EE_CLKC 42 42 tristate 43 43 select COMMON_CLK_MESON_REGMAP 44 + select COMMON_CLK_MESON_CLKC_UTILS 44 45 45 46 config COMMON_CLK_MESON_CPU_DYNDIV 46 47 tristate
+141 -142
drivers/clk/meson/axg.c
··· 1890 1890 1891 1891 /* Array of all clocks provided by this provider */ 1892 1892 1893 - static struct clk_hw_onecell_data axg_hw_onecell_data = { 1894 - .hws = { 1895 - [CLKID_SYS_PLL] = &axg_sys_pll.hw, 1896 - [CLKID_FIXED_PLL] = &axg_fixed_pll.hw, 1897 - [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw, 1898 - [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw, 1899 - [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw, 1900 - [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw, 1901 - [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw, 1902 - [CLKID_GP0_PLL] = &axg_gp0_pll.hw, 1903 - [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw, 1904 - [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw, 1905 - [CLKID_CLK81] = &axg_clk81.hw, 1906 - [CLKID_MPLL0] = &axg_mpll0.hw, 1907 - [CLKID_MPLL1] = &axg_mpll1.hw, 1908 - [CLKID_MPLL2] = &axg_mpll2.hw, 1909 - [CLKID_MPLL3] = &axg_mpll3.hw, 1910 - [CLKID_DDR] = &axg_ddr.hw, 1911 - [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw, 1912 - [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw, 1913 - [CLKID_ISA] = &axg_isa.hw, 1914 - [CLKID_PL301] = &axg_pl301.hw, 1915 - [CLKID_PERIPHS] = &axg_periphs.hw, 1916 - [CLKID_SPICC0] = &axg_spicc_0.hw, 1917 - [CLKID_I2C] = &axg_i2c.hw, 1918 - [CLKID_RNG0] = &axg_rng0.hw, 1919 - [CLKID_UART0] = &axg_uart0.hw, 1920 - [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw, 1921 - [CLKID_SPICC1] = &axg_spicc_1.hw, 1922 - [CLKID_PCIE_A] = &axg_pcie_a.hw, 1923 - [CLKID_PCIE_B] = &axg_pcie_b.hw, 1924 - [CLKID_HIU_IFACE] = &axg_hiu_reg.hw, 1925 - [CLKID_ASSIST_MISC] = &axg_assist_misc.hw, 1926 - [CLKID_SD_EMMC_B] = &axg_emmc_b.hw, 1927 - [CLKID_SD_EMMC_C] = &axg_emmc_c.hw, 1928 - [CLKID_DMA] = &axg_dma.hw, 1929 - [CLKID_SPI] = &axg_spi.hw, 1930 - [CLKID_AUDIO] = &axg_audio.hw, 1931 - [CLKID_ETH] = &axg_eth_core.hw, 1932 - [CLKID_UART1] = &axg_uart1.hw, 1933 - [CLKID_G2D] = &axg_g2d.hw, 1934 - [CLKID_USB0] = &axg_usb0.hw, 1935 - [CLKID_USB1] = &axg_usb1.hw, 1936 - [CLKID_RESET] = &axg_reset.hw, 1937 - [CLKID_USB] = &axg_usb_general.hw, 1938 - [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw, 1939 - [CLKID_EFUSE] = &axg_efuse.hw, 1940 - [CLKID_BOOT_ROM] = &axg_boot_rom.hw, 1941 - [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw, 1942 - [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw, 1943 - [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw, 1944 - [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw, 1945 - [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw, 1946 - [CLKID_VPU_INTR] = &axg_vpu_intr.hw, 1947 - [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw, 1948 - [CLKID_GIC] = &axg_gic.hw, 1949 - [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw, 1950 - [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw, 1951 - [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw, 1952 - [CLKID_AO_IFACE] = &axg_ao_iface.hw, 1953 - [CLKID_AO_I2C] = &axg_ao_i2c.hw, 1954 - [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw, 1955 - [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw, 1956 - [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw, 1957 - [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, 1958 - [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, 1959 - [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, 1960 - [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw, 1961 - [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw, 1962 - [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, 1963 - [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, 1964 - [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, 1965 - [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw, 1966 - [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw, 1967 - [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw, 1968 - [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw, 1969 - [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw, 1970 - [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw, 1971 - [CLKID_PCIE_PLL] = &axg_pcie_pll.hw, 1972 - [CLKID_PCIE_MUX] = &axg_pcie_mux.hw, 1973 - [CLKID_PCIE_REF] = &axg_pcie_ref.hw, 1974 - [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw, 1975 - [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw, 1976 - [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, 1977 - [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, 1978 - [CLKID_GEN_CLK] = &axg_gen_clk.hw, 1979 - [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw, 1980 - [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw, 1981 - [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw, 1982 - [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, 1983 - [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, 1984 - [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, 1985 - [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw, 1986 - [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw, 1987 - [CLKID_VPU_0] = &axg_vpu_0.hw, 1988 - [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw, 1989 - [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw, 1990 - [CLKID_VPU_1] = &axg_vpu_1.hw, 1991 - [CLKID_VPU] = &axg_vpu.hw, 1992 - [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw, 1993 - [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw, 1994 - [CLKID_VAPB_0] = &axg_vapb_0.hw, 1995 - [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw, 1996 - [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw, 1997 - [CLKID_VAPB_1] = &axg_vapb_1.hw, 1998 - [CLKID_VAPB_SEL] = &axg_vapb_sel.hw, 1999 - [CLKID_VAPB] = &axg_vapb.hw, 2000 - [CLKID_VCLK] = &axg_vclk.hw, 2001 - [CLKID_VCLK2] = &axg_vclk2.hw, 2002 - [CLKID_VCLK_SEL] = &axg_vclk_sel.hw, 2003 - [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw, 2004 - [CLKID_VCLK_INPUT] = &axg_vclk_input.hw, 2005 - [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw, 2006 - [CLKID_VCLK_DIV] = &axg_vclk_div.hw, 2007 - [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw, 2008 - [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw, 2009 - [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw, 2010 - [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw, 2011 - [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw, 2012 - [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw, 2013 - [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw, 2014 - [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw, 2015 - [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw, 2016 - [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw, 2017 - [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw, 2018 - [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw, 2019 - [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw, 2020 - [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw, 2021 - [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw, 2022 - [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw, 2023 - [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw, 2024 - [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw, 2025 - [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw, 2026 - [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw, 2027 - [CLKID_CTS_ENCL] = &axg_cts_encl.hw, 2028 - [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw, 2029 - [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw, 2030 - [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw, 2031 - [NR_CLKS] = NULL, 2032 - }, 2033 - .num = NR_CLKS, 1893 + static struct clk_hw *axg_hw_clks[] = { 1894 + [CLKID_SYS_PLL] = &axg_sys_pll.hw, 1895 + [CLKID_FIXED_PLL] = &axg_fixed_pll.hw, 1896 + [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw, 1897 + [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw, 1898 + [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw, 1899 + [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw, 1900 + [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw, 1901 + [CLKID_GP0_PLL] = &axg_gp0_pll.hw, 1902 + [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw, 1903 + [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw, 1904 + [CLKID_CLK81] = &axg_clk81.hw, 1905 + [CLKID_MPLL0] = &axg_mpll0.hw, 1906 + [CLKID_MPLL1] = &axg_mpll1.hw, 1907 + [CLKID_MPLL2] = &axg_mpll2.hw, 1908 + [CLKID_MPLL3] = &axg_mpll3.hw, 1909 + [CLKID_DDR] = &axg_ddr.hw, 1910 + [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw, 1911 + [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw, 1912 + [CLKID_ISA] = &axg_isa.hw, 1913 + [CLKID_PL301] = &axg_pl301.hw, 1914 + [CLKID_PERIPHS] = &axg_periphs.hw, 1915 + [CLKID_SPICC0] = &axg_spicc_0.hw, 1916 + [CLKID_I2C] = &axg_i2c.hw, 1917 + [CLKID_RNG0] = &axg_rng0.hw, 1918 + [CLKID_UART0] = &axg_uart0.hw, 1919 + [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw, 1920 + [CLKID_SPICC1] = &axg_spicc_1.hw, 1921 + [CLKID_PCIE_A] = &axg_pcie_a.hw, 1922 + [CLKID_PCIE_B] = &axg_pcie_b.hw, 1923 + [CLKID_HIU_IFACE] = &axg_hiu_reg.hw, 1924 + [CLKID_ASSIST_MISC] = &axg_assist_misc.hw, 1925 + [CLKID_SD_EMMC_B] = &axg_emmc_b.hw, 1926 + [CLKID_SD_EMMC_C] = &axg_emmc_c.hw, 1927 + [CLKID_DMA] = &axg_dma.hw, 1928 + [CLKID_SPI] = &axg_spi.hw, 1929 + [CLKID_AUDIO] = &axg_audio.hw, 1930 + [CLKID_ETH] = &axg_eth_core.hw, 1931 + [CLKID_UART1] = &axg_uart1.hw, 1932 + [CLKID_G2D] = &axg_g2d.hw, 1933 + [CLKID_USB0] = &axg_usb0.hw, 1934 + [CLKID_USB1] = &axg_usb1.hw, 1935 + [CLKID_RESET] = &axg_reset.hw, 1936 + [CLKID_USB] = &axg_usb_general.hw, 1937 + [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw, 1938 + [CLKID_EFUSE] = &axg_efuse.hw, 1939 + [CLKID_BOOT_ROM] = &axg_boot_rom.hw, 1940 + [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw, 1941 + [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw, 1942 + [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw, 1943 + [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw, 1944 + [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw, 1945 + [CLKID_VPU_INTR] = &axg_vpu_intr.hw, 1946 + [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw, 1947 + [CLKID_GIC] = &axg_gic.hw, 1948 + [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw, 1949 + [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw, 1950 + [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw, 1951 + [CLKID_AO_IFACE] = &axg_ao_iface.hw, 1952 + [CLKID_AO_I2C] = &axg_ao_i2c.hw, 1953 + [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw, 1954 + [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw, 1955 + [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw, 1956 + [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, 1957 + [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, 1958 + [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, 1959 + [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw, 1960 + [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw, 1961 + [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, 1962 + [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, 1963 + [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, 1964 + [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw, 1965 + [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw, 1966 + [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw, 1967 + [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw, 1968 + [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw, 1969 + [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw, 1970 + [CLKID_PCIE_PLL] = &axg_pcie_pll.hw, 1971 + [CLKID_PCIE_MUX] = &axg_pcie_mux.hw, 1972 + [CLKID_PCIE_REF] = &axg_pcie_ref.hw, 1973 + [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw, 1974 + [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw, 1975 + [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, 1976 + [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, 1977 + [CLKID_GEN_CLK] = &axg_gen_clk.hw, 1978 + [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw, 1979 + [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw, 1980 + [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw, 1981 + [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, 1982 + [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, 1983 + [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, 1984 + [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw, 1985 + [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw, 1986 + [CLKID_VPU_0] = &axg_vpu_0.hw, 1987 + [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw, 1988 + [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw, 1989 + [CLKID_VPU_1] = &axg_vpu_1.hw, 1990 + [CLKID_VPU] = &axg_vpu.hw, 1991 + [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw, 1992 + [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw, 1993 + [CLKID_VAPB_0] = &axg_vapb_0.hw, 1994 + [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw, 1995 + [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw, 1996 + [CLKID_VAPB_1] = &axg_vapb_1.hw, 1997 + [CLKID_VAPB_SEL] = &axg_vapb_sel.hw, 1998 + [CLKID_VAPB] = &axg_vapb.hw, 1999 + [CLKID_VCLK] = &axg_vclk.hw, 2000 + [CLKID_VCLK2] = &axg_vclk2.hw, 2001 + [CLKID_VCLK_SEL] = &axg_vclk_sel.hw, 2002 + [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw, 2003 + [CLKID_VCLK_INPUT] = &axg_vclk_input.hw, 2004 + [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw, 2005 + [CLKID_VCLK_DIV] = &axg_vclk_div.hw, 2006 + [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw, 2007 + [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw, 2008 + [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw, 2009 + [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw, 2010 + [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw, 2011 + [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw, 2012 + [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw, 2013 + [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw, 2014 + [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw, 2015 + [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw, 2016 + [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw, 2017 + [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw, 2018 + [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw, 2019 + [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw, 2020 + [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw, 2021 + [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw, 2022 + [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw, 2023 + [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw, 2024 + [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw, 2025 + [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw, 2026 + [CLKID_CTS_ENCL] = &axg_cts_encl.hw, 2027 + [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw, 2028 + [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw, 2029 + [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw, 2034 2030 }; 2035 2031 2036 2032 /* Convenience table to populate regmap in .probe */ ··· 2159 2163 static const struct meson_eeclkc_data axg_clkc_data = { 2160 2164 .regmap_clks = axg_clk_regmaps, 2161 2165 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), 2162 - .hw_onecell_data = &axg_hw_onecell_data, 2166 + .hw_clks = { 2167 + .hws = axg_hw_clks, 2168 + .num = ARRAY_SIZE(axg_hw_clks), 2169 + }, 2163 2170 }; 2164 2171 2165 2172
-2
drivers/clk/meson/axg.h
··· 160 160 #define CLKID_VDIN_MEAS_SEL 134 161 161 #define CLKID_VDIN_MEAS_DIV 135 162 162 163 - #define NR_CLKS 137 164 - 165 163 /* include the CLKIDs that have been made part of the DT binding */ 166 164 #include <dt-bindings/clock/axg-clkc.h> 167 165
+738 -741
drivers/clk/meson/g12a.c
··· 4244 4244 static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4); 4245 4245 4246 4246 /* Array of all clocks provided by this provider */ 4247 - static struct clk_hw_onecell_data g12a_hw_onecell_data = { 4248 - .hws = { 4249 - [CLKID_SYS_PLL] = &g12a_sys_pll.hw, 4250 - [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw, 4251 - [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw, 4252 - [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw, 4253 - [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw, 4254 - [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw, 4255 - [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, 4256 - [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, 4257 - [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, 4258 - [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, 4259 - [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, 4260 - [CLKID_CLK81] = &g12a_clk81.hw, 4261 - [CLKID_MPLL0] = &g12a_mpll0.hw, 4262 - [CLKID_MPLL1] = &g12a_mpll1.hw, 4263 - [CLKID_MPLL2] = &g12a_mpll2.hw, 4264 - [CLKID_MPLL3] = &g12a_mpll3.hw, 4265 - [CLKID_DDR] = &g12a_ddr.hw, 4266 - [CLKID_DOS] = &g12a_dos.hw, 4267 - [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw, 4268 - [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw, 4269 - [CLKID_ETH_PHY] = &g12a_eth_phy.hw, 4270 - [CLKID_ISA] = &g12a_isa.hw, 4271 - [CLKID_PL301] = &g12a_pl301.hw, 4272 - [CLKID_PERIPHS] = &g12a_periphs.hw, 4273 - [CLKID_SPICC0] = &g12a_spicc_0.hw, 4274 - [CLKID_I2C] = &g12a_i2c.hw, 4275 - [CLKID_SANA] = &g12a_sana.hw, 4276 - [CLKID_SD] = &g12a_sd.hw, 4277 - [CLKID_RNG0] = &g12a_rng0.hw, 4278 - [CLKID_UART0] = &g12a_uart0.hw, 4279 - [CLKID_SPICC1] = &g12a_spicc_1.hw, 4280 - [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw, 4281 - [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw, 4282 - [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw, 4283 - [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw, 4284 - [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw, 4285 - [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw, 4286 - [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw, 4287 - [CLKID_AUDIO] = &g12a_audio.hw, 4288 - [CLKID_ETH] = &g12a_eth_core.hw, 4289 - [CLKID_DEMUX] = &g12a_demux.hw, 4290 - [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw, 4291 - [CLKID_ADC] = &g12a_adc.hw, 4292 - [CLKID_UART1] = &g12a_uart1.hw, 4293 - [CLKID_G2D] = &g12a_g2d.hw, 4294 - [CLKID_RESET] = &g12a_reset.hw, 4295 - [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw, 4296 - [CLKID_PARSER] = &g12a_parser.hw, 4297 - [CLKID_USB] = &g12a_usb_general.hw, 4298 - [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw, 4299 - [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw, 4300 - [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw, 4301 - [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw, 4302 - [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw, 4303 - [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw, 4304 - [CLKID_BT656] = &g12a_bt656.hw, 4305 - [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw, 4306 - [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw, 4307 - [CLKID_UART2] = &g12a_uart2.hw, 4308 - [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, 4309 - [CLKID_GIC] = &g12a_gic.hw, 4310 - [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, 4311 - [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, 4312 - [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, 4313 - [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, 4314 - [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, 4315 - [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, 4316 - [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, 4317 - [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, 4318 - [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, 4319 - [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, 4320 - [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, 4321 - [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, 4322 - [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, 4323 - [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, 4324 - [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, 4325 - [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, 4326 - [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, 4327 - [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, 4328 - [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, 4329 - [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, 4330 - [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, 4331 - [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, 4332 - [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw, 4333 - [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw, 4334 - [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw, 4335 - [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw, 4336 - [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw, 4337 - [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw, 4338 - [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw, 4339 - [CLKID_DAC_CLK] = &g12a_dac_clk.hw, 4340 - [CLKID_AOCLK] = &g12a_aoclk_gate.hw, 4341 - [CLKID_IEC958] = &g12a_iec958_gate.hw, 4342 - [CLKID_ENC480P] = &g12a_enc480p.hw, 4343 - [CLKID_RNG1] = &g12a_rng1.hw, 4344 - [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw, 4345 - [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw, 4346 - [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, 4347 - [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, 4348 - [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, 4349 - [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, 4350 - [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, 4351 - [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, 4352 - [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, 4353 - [CLKID_DMA] = &g12a_dma.hw, 4354 - [CLKID_EFUSE] = &g12a_efuse.hw, 4355 - [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, 4356 - [CLKID_RESET_SEC] = &g12a_reset_sec.hw, 4357 - [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, 4358 - [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, 4359 - [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, 4360 - [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, 4361 - [CLKID_VPU_0] = &g12a_vpu_0.hw, 4362 - [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, 4363 - [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, 4364 - [CLKID_VPU_1] = &g12a_vpu_1.hw, 4365 - [CLKID_VPU] = &g12a_vpu.hw, 4366 - [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, 4367 - [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, 4368 - [CLKID_VAPB_0] = &g12a_vapb_0.hw, 4369 - [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, 4370 - [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, 4371 - [CLKID_VAPB_1] = &g12a_vapb_1.hw, 4372 - [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, 4373 - [CLKID_VAPB] = &g12a_vapb.hw, 4374 - [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, 4375 - [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, 4376 - [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, 4377 - [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, 4378 - [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, 4379 - [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, 4380 - [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, 4381 - [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, 4382 - [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, 4383 - [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, 4384 - [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, 4385 - [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, 4386 - [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, 4387 - [CLKID_VCLK] = &g12a_vclk.hw, 4388 - [CLKID_VCLK2] = &g12a_vclk2.hw, 4389 - [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, 4390 - [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, 4391 - [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, 4392 - [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, 4393 - [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, 4394 - [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, 4395 - [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, 4396 - [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, 4397 - [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, 4398 - [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, 4399 - [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, 4400 - [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, 4401 - [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, 4402 - [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw, 4403 - [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw, 4404 - [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, 4405 - [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, 4406 - [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, 4407 - [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, 4408 - [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, 4409 - [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, 4410 - [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, 4411 - [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, 4412 - [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, 4413 - [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, 4414 - [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, 4415 - [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, 4416 - [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, 4417 - [CLKID_HDMI] = &g12a_hdmi.hw, 4418 - [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, 4419 - [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, 4420 - [CLKID_MALI_0] = &g12a_mali_0.hw, 4421 - [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, 4422 - [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, 4423 - [CLKID_MALI_1] = &g12a_mali_1.hw, 4424 - [CLKID_MALI] = &g12a_mali.hw, 4425 - [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, 4426 - [CLKID_MPLL_50M] = &g12a_mpll_50m.hw, 4427 - [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, 4428 - [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, 4429 - [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, 4430 - [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, 4431 - [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, 4432 - [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, 4433 - [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, 4434 - [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, 4435 - [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, 4436 - [CLKID_CPU_CLK] = &g12a_cpu_clk.hw, 4437 - [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, 4438 - [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, 4439 - [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, 4440 - [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, 4441 - [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, 4442 - [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, 4443 - [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, 4444 - [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, 4445 - [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, 4446 - [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, 4447 - [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, 4448 - [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, 4449 - [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, 4450 - [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, 4451 - [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, 4452 - [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, 4453 - [CLKID_VDEC_1] = &g12a_vdec_1.hw, 4454 - [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, 4455 - [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, 4456 - [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, 4457 - [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, 4458 - [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, 4459 - [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, 4460 - [CLKID_TS_DIV] = &g12a_ts_div.hw, 4461 - [CLKID_TS] = &g12a_ts.hw, 4462 - [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, 4463 - [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, 4464 - [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, 4465 - [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, 4466 - [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, 4467 - [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, 4468 - [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw, 4469 - [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, 4470 - [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, 4471 - [NR_CLKS] = NULL, 4472 - }, 4473 - .num = NR_CLKS, 4247 + static struct clk_hw *g12a_hw_clks[] = { 4248 + [CLKID_SYS_PLL] = &g12a_sys_pll.hw, 4249 + [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw, 4250 + [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw, 4251 + [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw, 4252 + [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw, 4253 + [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw, 4254 + [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, 4255 + [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, 4256 + [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, 4257 + [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, 4258 + [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, 4259 + [CLKID_CLK81] = &g12a_clk81.hw, 4260 + [CLKID_MPLL0] = &g12a_mpll0.hw, 4261 + [CLKID_MPLL1] = &g12a_mpll1.hw, 4262 + [CLKID_MPLL2] = &g12a_mpll2.hw, 4263 + [CLKID_MPLL3] = &g12a_mpll3.hw, 4264 + [CLKID_DDR] = &g12a_ddr.hw, 4265 + [CLKID_DOS] = &g12a_dos.hw, 4266 + [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw, 4267 + [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw, 4268 + [CLKID_ETH_PHY] = &g12a_eth_phy.hw, 4269 + [CLKID_ISA] = &g12a_isa.hw, 4270 + [CLKID_PL301] = &g12a_pl301.hw, 4271 + [CLKID_PERIPHS] = &g12a_periphs.hw, 4272 + [CLKID_SPICC0] = &g12a_spicc_0.hw, 4273 + [CLKID_I2C] = &g12a_i2c.hw, 4274 + [CLKID_SANA] = &g12a_sana.hw, 4275 + [CLKID_SD] = &g12a_sd.hw, 4276 + [CLKID_RNG0] = &g12a_rng0.hw, 4277 + [CLKID_UART0] = &g12a_uart0.hw, 4278 + [CLKID_SPICC1] = &g12a_spicc_1.hw, 4279 + [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw, 4280 + [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw, 4281 + [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw, 4282 + [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw, 4283 + [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw, 4284 + [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw, 4285 + [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw, 4286 + [CLKID_AUDIO] = &g12a_audio.hw, 4287 + [CLKID_ETH] = &g12a_eth_core.hw, 4288 + [CLKID_DEMUX] = &g12a_demux.hw, 4289 + [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw, 4290 + [CLKID_ADC] = &g12a_adc.hw, 4291 + [CLKID_UART1] = &g12a_uart1.hw, 4292 + [CLKID_G2D] = &g12a_g2d.hw, 4293 + [CLKID_RESET] = &g12a_reset.hw, 4294 + [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw, 4295 + [CLKID_PARSER] = &g12a_parser.hw, 4296 + [CLKID_USB] = &g12a_usb_general.hw, 4297 + [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw, 4298 + [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw, 4299 + [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw, 4300 + [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw, 4301 + [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw, 4302 + [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw, 4303 + [CLKID_BT656] = &g12a_bt656.hw, 4304 + [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw, 4305 + [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw, 4306 + [CLKID_UART2] = &g12a_uart2.hw, 4307 + [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, 4308 + [CLKID_GIC] = &g12a_gic.hw, 4309 + [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, 4310 + [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, 4311 + [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, 4312 + [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, 4313 + [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, 4314 + [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, 4315 + [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, 4316 + [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, 4317 + [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, 4318 + [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, 4319 + [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, 4320 + [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, 4321 + [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, 4322 + [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, 4323 + [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, 4324 + [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, 4325 + [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, 4326 + [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, 4327 + [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, 4328 + [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, 4329 + [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, 4330 + [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, 4331 + [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw, 4332 + [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw, 4333 + [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw, 4334 + [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw, 4335 + [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw, 4336 + [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw, 4337 + [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw, 4338 + [CLKID_DAC_CLK] = &g12a_dac_clk.hw, 4339 + [CLKID_AOCLK] = &g12a_aoclk_gate.hw, 4340 + [CLKID_IEC958] = &g12a_iec958_gate.hw, 4341 + [CLKID_ENC480P] = &g12a_enc480p.hw, 4342 + [CLKID_RNG1] = &g12a_rng1.hw, 4343 + [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw, 4344 + [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw, 4345 + [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, 4346 + [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, 4347 + [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, 4348 + [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, 4349 + [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, 4350 + [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, 4351 + [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, 4352 + [CLKID_DMA] = &g12a_dma.hw, 4353 + [CLKID_EFUSE] = &g12a_efuse.hw, 4354 + [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, 4355 + [CLKID_RESET_SEC] = &g12a_reset_sec.hw, 4356 + [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, 4357 + [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, 4358 + [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, 4359 + [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, 4360 + [CLKID_VPU_0] = &g12a_vpu_0.hw, 4361 + [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, 4362 + [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, 4363 + [CLKID_VPU_1] = &g12a_vpu_1.hw, 4364 + [CLKID_VPU] = &g12a_vpu.hw, 4365 + [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, 4366 + [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, 4367 + [CLKID_VAPB_0] = &g12a_vapb_0.hw, 4368 + [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, 4369 + [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, 4370 + [CLKID_VAPB_1] = &g12a_vapb_1.hw, 4371 + [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, 4372 + [CLKID_VAPB] = &g12a_vapb.hw, 4373 + [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, 4374 + [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, 4375 + [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, 4376 + [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, 4377 + [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, 4378 + [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, 4379 + [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, 4380 + [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, 4381 + [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, 4382 + [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, 4383 + [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, 4384 + [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, 4385 + [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, 4386 + [CLKID_VCLK] = &g12a_vclk.hw, 4387 + [CLKID_VCLK2] = &g12a_vclk2.hw, 4388 + [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, 4389 + [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, 4390 + [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, 4391 + [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, 4392 + [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, 4393 + [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, 4394 + [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, 4395 + [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, 4396 + [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, 4397 + [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, 4398 + [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, 4399 + [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, 4400 + [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, 4401 + [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw, 4402 + [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw, 4403 + [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, 4404 + [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, 4405 + [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, 4406 + [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, 4407 + [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, 4408 + [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, 4409 + [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, 4410 + [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, 4411 + [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, 4412 + [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, 4413 + [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, 4414 + [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, 4415 + [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, 4416 + [CLKID_HDMI] = &g12a_hdmi.hw, 4417 + [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, 4418 + [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, 4419 + [CLKID_MALI_0] = &g12a_mali_0.hw, 4420 + [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, 4421 + [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, 4422 + [CLKID_MALI_1] = &g12a_mali_1.hw, 4423 + [CLKID_MALI] = &g12a_mali.hw, 4424 + [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, 4425 + [CLKID_MPLL_50M] = &g12a_mpll_50m.hw, 4426 + [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, 4427 + [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, 4428 + [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, 4429 + [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, 4430 + [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, 4431 + [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, 4432 + [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, 4433 + [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, 4434 + [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, 4435 + [CLKID_CPU_CLK] = &g12a_cpu_clk.hw, 4436 + [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, 4437 + [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, 4438 + [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, 4439 + [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, 4440 + [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, 4441 + [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, 4442 + [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, 4443 + [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, 4444 + [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, 4445 + [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, 4446 + [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, 4447 + [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, 4448 + [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, 4449 + [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, 4450 + [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, 4451 + [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, 4452 + [CLKID_VDEC_1] = &g12a_vdec_1.hw, 4453 + [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, 4454 + [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, 4455 + [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, 4456 + [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, 4457 + [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, 4458 + [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, 4459 + [CLKID_TS_DIV] = &g12a_ts_div.hw, 4460 + [CLKID_TS] = &g12a_ts.hw, 4461 + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, 4462 + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, 4463 + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, 4464 + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, 4465 + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, 4466 + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, 4467 + [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw, 4468 + [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, 4469 + [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, 4474 4470 }; 4475 4471 4476 - static struct clk_hw_onecell_data g12b_hw_onecell_data = { 4477 - .hws = { 4478 - [CLKID_SYS_PLL] = &g12a_sys_pll.hw, 4479 - [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw, 4480 - [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw, 4481 - [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw, 4482 - [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw, 4483 - [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw, 4484 - [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, 4485 - [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, 4486 - [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, 4487 - [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, 4488 - [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, 4489 - [CLKID_CLK81] = &g12a_clk81.hw, 4490 - [CLKID_MPLL0] = &g12a_mpll0.hw, 4491 - [CLKID_MPLL1] = &g12a_mpll1.hw, 4492 - [CLKID_MPLL2] = &g12a_mpll2.hw, 4493 - [CLKID_MPLL3] = &g12a_mpll3.hw, 4494 - [CLKID_DDR] = &g12a_ddr.hw, 4495 - [CLKID_DOS] = &g12a_dos.hw, 4496 - [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw, 4497 - [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw, 4498 - [CLKID_ETH_PHY] = &g12a_eth_phy.hw, 4499 - [CLKID_ISA] = &g12a_isa.hw, 4500 - [CLKID_PL301] = &g12a_pl301.hw, 4501 - [CLKID_PERIPHS] = &g12a_periphs.hw, 4502 - [CLKID_SPICC0] = &g12a_spicc_0.hw, 4503 - [CLKID_I2C] = &g12a_i2c.hw, 4504 - [CLKID_SANA] = &g12a_sana.hw, 4505 - [CLKID_SD] = &g12a_sd.hw, 4506 - [CLKID_RNG0] = &g12a_rng0.hw, 4507 - [CLKID_UART0] = &g12a_uart0.hw, 4508 - [CLKID_SPICC1] = &g12a_spicc_1.hw, 4509 - [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw, 4510 - [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw, 4511 - [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw, 4512 - [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw, 4513 - [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw, 4514 - [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw, 4515 - [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw, 4516 - [CLKID_AUDIO] = &g12a_audio.hw, 4517 - [CLKID_ETH] = &g12a_eth_core.hw, 4518 - [CLKID_DEMUX] = &g12a_demux.hw, 4519 - [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw, 4520 - [CLKID_ADC] = &g12a_adc.hw, 4521 - [CLKID_UART1] = &g12a_uart1.hw, 4522 - [CLKID_G2D] = &g12a_g2d.hw, 4523 - [CLKID_RESET] = &g12a_reset.hw, 4524 - [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw, 4525 - [CLKID_PARSER] = &g12a_parser.hw, 4526 - [CLKID_USB] = &g12a_usb_general.hw, 4527 - [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw, 4528 - [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw, 4529 - [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw, 4530 - [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw, 4531 - [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw, 4532 - [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw, 4533 - [CLKID_BT656] = &g12a_bt656.hw, 4534 - [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw, 4535 - [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw, 4536 - [CLKID_UART2] = &g12a_uart2.hw, 4537 - [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, 4538 - [CLKID_GIC] = &g12a_gic.hw, 4539 - [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, 4540 - [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, 4541 - [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, 4542 - [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, 4543 - [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, 4544 - [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, 4545 - [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, 4546 - [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, 4547 - [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, 4548 - [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, 4549 - [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, 4550 - [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, 4551 - [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, 4552 - [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, 4553 - [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, 4554 - [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, 4555 - [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, 4556 - [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, 4557 - [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, 4558 - [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, 4559 - [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, 4560 - [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, 4561 - [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw, 4562 - [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw, 4563 - [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw, 4564 - [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw, 4565 - [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw, 4566 - [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw, 4567 - [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw, 4568 - [CLKID_DAC_CLK] = &g12a_dac_clk.hw, 4569 - [CLKID_AOCLK] = &g12a_aoclk_gate.hw, 4570 - [CLKID_IEC958] = &g12a_iec958_gate.hw, 4571 - [CLKID_ENC480P] = &g12a_enc480p.hw, 4572 - [CLKID_RNG1] = &g12a_rng1.hw, 4573 - [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw, 4574 - [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw, 4575 - [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, 4576 - [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, 4577 - [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, 4578 - [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, 4579 - [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, 4580 - [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, 4581 - [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, 4582 - [CLKID_DMA] = &g12a_dma.hw, 4583 - [CLKID_EFUSE] = &g12a_efuse.hw, 4584 - [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, 4585 - [CLKID_RESET_SEC] = &g12a_reset_sec.hw, 4586 - [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, 4587 - [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, 4588 - [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, 4589 - [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, 4590 - [CLKID_VPU_0] = &g12a_vpu_0.hw, 4591 - [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, 4592 - [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, 4593 - [CLKID_VPU_1] = &g12a_vpu_1.hw, 4594 - [CLKID_VPU] = &g12a_vpu.hw, 4595 - [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, 4596 - [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, 4597 - [CLKID_VAPB_0] = &g12a_vapb_0.hw, 4598 - [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, 4599 - [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, 4600 - [CLKID_VAPB_1] = &g12a_vapb_1.hw, 4601 - [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, 4602 - [CLKID_VAPB] = &g12a_vapb.hw, 4603 - [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, 4604 - [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, 4605 - [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, 4606 - [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, 4607 - [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, 4608 - [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, 4609 - [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, 4610 - [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, 4611 - [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, 4612 - [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, 4613 - [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, 4614 - [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, 4615 - [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, 4616 - [CLKID_VCLK] = &g12a_vclk.hw, 4617 - [CLKID_VCLK2] = &g12a_vclk2.hw, 4618 - [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, 4619 - [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, 4620 - [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, 4621 - [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, 4622 - [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, 4623 - [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, 4624 - [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, 4625 - [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, 4626 - [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, 4627 - [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, 4628 - [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, 4629 - [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, 4630 - [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, 4631 - [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw, 4632 - [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw, 4633 - [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, 4634 - [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, 4635 - [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, 4636 - [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, 4637 - [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, 4638 - [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, 4639 - [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, 4640 - [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, 4641 - [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, 4642 - [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, 4643 - [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, 4644 - [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, 4645 - [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, 4646 - [CLKID_HDMI] = &g12a_hdmi.hw, 4647 - [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, 4648 - [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, 4649 - [CLKID_MALI_0] = &g12a_mali_0.hw, 4650 - [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, 4651 - [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, 4652 - [CLKID_MALI_1] = &g12a_mali_1.hw, 4653 - [CLKID_MALI] = &g12a_mali.hw, 4654 - [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, 4655 - [CLKID_MPLL_50M] = &g12a_mpll_50m.hw, 4656 - [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, 4657 - [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, 4658 - [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, 4659 - [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, 4660 - [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, 4661 - [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, 4662 - [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, 4663 - [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, 4664 - [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, 4665 - [CLKID_CPU_CLK] = &g12b_cpu_clk.hw, 4666 - [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, 4667 - [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, 4668 - [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, 4669 - [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, 4670 - [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, 4671 - [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, 4672 - [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, 4673 - [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, 4674 - [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, 4675 - [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, 4676 - [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, 4677 - [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, 4678 - [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, 4679 - [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, 4680 - [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, 4681 - [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, 4682 - [CLKID_VDEC_1] = &g12a_vdec_1.hw, 4683 - [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, 4684 - [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, 4685 - [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, 4686 - [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, 4687 - [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, 4688 - [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, 4689 - [CLKID_TS_DIV] = &g12a_ts_div.hw, 4690 - [CLKID_TS] = &g12a_ts.hw, 4691 - [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw, 4692 - [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw, 4693 - [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw, 4694 - [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw, 4695 - [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw, 4696 - [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw, 4697 - [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw, 4698 - [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw, 4699 - [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw, 4700 - [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw, 4701 - [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw, 4702 - [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw, 4703 - [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw, 4704 - [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw, 4705 - [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw, 4706 - [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw, 4707 - [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw, 4708 - [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw, 4709 - [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw, 4710 - [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw, 4711 - [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw, 4712 - [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw, 4713 - [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw, 4714 - [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw, 4715 - [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw, 4716 - [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw, 4717 - [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw, 4718 - [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw, 4719 - [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw, 4720 - [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, 4721 - [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, 4722 - [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, 4723 - [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, 4724 - [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, 4725 - [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, 4726 - [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw, 4727 - [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw, 4728 - [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw, 4729 - [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw, 4730 - [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw, 4731 - [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw, 4732 - [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw, 4733 - [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, 4734 - [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, 4735 - [NR_CLKS] = NULL, 4736 - }, 4737 - .num = NR_CLKS, 4472 + static struct clk_hw *g12b_hw_clks[] = { 4473 + [CLKID_SYS_PLL] = &g12a_sys_pll.hw, 4474 + [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw, 4475 + [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw, 4476 + [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw, 4477 + [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw, 4478 + [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw, 4479 + [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, 4480 + [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, 4481 + [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, 4482 + [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, 4483 + [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, 4484 + [CLKID_CLK81] = &g12a_clk81.hw, 4485 + [CLKID_MPLL0] = &g12a_mpll0.hw, 4486 + [CLKID_MPLL1] = &g12a_mpll1.hw, 4487 + [CLKID_MPLL2] = &g12a_mpll2.hw, 4488 + [CLKID_MPLL3] = &g12a_mpll3.hw, 4489 + [CLKID_DDR] = &g12a_ddr.hw, 4490 + [CLKID_DOS] = &g12a_dos.hw, 4491 + [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw, 4492 + [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw, 4493 + [CLKID_ETH_PHY] = &g12a_eth_phy.hw, 4494 + [CLKID_ISA] = &g12a_isa.hw, 4495 + [CLKID_PL301] = &g12a_pl301.hw, 4496 + [CLKID_PERIPHS] = &g12a_periphs.hw, 4497 + [CLKID_SPICC0] = &g12a_spicc_0.hw, 4498 + [CLKID_I2C] = &g12a_i2c.hw, 4499 + [CLKID_SANA] = &g12a_sana.hw, 4500 + [CLKID_SD] = &g12a_sd.hw, 4501 + [CLKID_RNG0] = &g12a_rng0.hw, 4502 + [CLKID_UART0] = &g12a_uart0.hw, 4503 + [CLKID_SPICC1] = &g12a_spicc_1.hw, 4504 + [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw, 4505 + [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw, 4506 + [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw, 4507 + [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw, 4508 + [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw, 4509 + [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw, 4510 + [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw, 4511 + [CLKID_AUDIO] = &g12a_audio.hw, 4512 + [CLKID_ETH] = &g12a_eth_core.hw, 4513 + [CLKID_DEMUX] = &g12a_demux.hw, 4514 + [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw, 4515 + [CLKID_ADC] = &g12a_adc.hw, 4516 + [CLKID_UART1] = &g12a_uart1.hw, 4517 + [CLKID_G2D] = &g12a_g2d.hw, 4518 + [CLKID_RESET] = &g12a_reset.hw, 4519 + [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw, 4520 + [CLKID_PARSER] = &g12a_parser.hw, 4521 + [CLKID_USB] = &g12a_usb_general.hw, 4522 + [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw, 4523 + [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw, 4524 + [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw, 4525 + [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw, 4526 + [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw, 4527 + [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw, 4528 + [CLKID_BT656] = &g12a_bt656.hw, 4529 + [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw, 4530 + [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw, 4531 + [CLKID_UART2] = &g12a_uart2.hw, 4532 + [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, 4533 + [CLKID_GIC] = &g12a_gic.hw, 4534 + [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, 4535 + [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, 4536 + [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, 4537 + [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, 4538 + [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, 4539 + [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, 4540 + [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, 4541 + [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, 4542 + [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, 4543 + [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, 4544 + [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, 4545 + [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, 4546 + [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, 4547 + [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, 4548 + [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, 4549 + [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, 4550 + [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, 4551 + [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, 4552 + [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, 4553 + [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, 4554 + [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, 4555 + [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, 4556 + [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw, 4557 + [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw, 4558 + [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw, 4559 + [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw, 4560 + [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw, 4561 + [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw, 4562 + [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw, 4563 + [CLKID_DAC_CLK] = &g12a_dac_clk.hw, 4564 + [CLKID_AOCLK] = &g12a_aoclk_gate.hw, 4565 + [CLKID_IEC958] = &g12a_iec958_gate.hw, 4566 + [CLKID_ENC480P] = &g12a_enc480p.hw, 4567 + [CLKID_RNG1] = &g12a_rng1.hw, 4568 + [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw, 4569 + [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw, 4570 + [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, 4571 + [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, 4572 + [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, 4573 + [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, 4574 + [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, 4575 + [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, 4576 + [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, 4577 + [CLKID_DMA] = &g12a_dma.hw, 4578 + [CLKID_EFUSE] = &g12a_efuse.hw, 4579 + [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, 4580 + [CLKID_RESET_SEC] = &g12a_reset_sec.hw, 4581 + [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, 4582 + [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, 4583 + [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, 4584 + [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, 4585 + [CLKID_VPU_0] = &g12a_vpu_0.hw, 4586 + [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, 4587 + [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, 4588 + [CLKID_VPU_1] = &g12a_vpu_1.hw, 4589 + [CLKID_VPU] = &g12a_vpu.hw, 4590 + [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, 4591 + [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, 4592 + [CLKID_VAPB_0] = &g12a_vapb_0.hw, 4593 + [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, 4594 + [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, 4595 + [CLKID_VAPB_1] = &g12a_vapb_1.hw, 4596 + [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, 4597 + [CLKID_VAPB] = &g12a_vapb.hw, 4598 + [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, 4599 + [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, 4600 + [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, 4601 + [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, 4602 + [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, 4603 + [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, 4604 + [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, 4605 + [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, 4606 + [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, 4607 + [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, 4608 + [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, 4609 + [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, 4610 + [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, 4611 + [CLKID_VCLK] = &g12a_vclk.hw, 4612 + [CLKID_VCLK2] = &g12a_vclk2.hw, 4613 + [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, 4614 + [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, 4615 + [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, 4616 + [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, 4617 + [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, 4618 + [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, 4619 + [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, 4620 + [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, 4621 + [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, 4622 + [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, 4623 + [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, 4624 + [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, 4625 + [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, 4626 + [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw, 4627 + [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw, 4628 + [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, 4629 + [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, 4630 + [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, 4631 + [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, 4632 + [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, 4633 + [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, 4634 + [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, 4635 + [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, 4636 + [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, 4637 + [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, 4638 + [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, 4639 + [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, 4640 + [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, 4641 + [CLKID_HDMI] = &g12a_hdmi.hw, 4642 + [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, 4643 + [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, 4644 + [CLKID_MALI_0] = &g12a_mali_0.hw, 4645 + [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, 4646 + [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, 4647 + [CLKID_MALI_1] = &g12a_mali_1.hw, 4648 + [CLKID_MALI] = &g12a_mali.hw, 4649 + [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, 4650 + [CLKID_MPLL_50M] = &g12a_mpll_50m.hw, 4651 + [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, 4652 + [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, 4653 + [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, 4654 + [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, 4655 + [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, 4656 + [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, 4657 + [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, 4658 + [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, 4659 + [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, 4660 + [CLKID_CPU_CLK] = &g12b_cpu_clk.hw, 4661 + [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, 4662 + [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, 4663 + [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, 4664 + [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, 4665 + [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, 4666 + [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, 4667 + [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, 4668 + [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, 4669 + [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, 4670 + [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, 4671 + [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, 4672 + [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, 4673 + [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, 4674 + [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, 4675 + [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, 4676 + [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, 4677 + [CLKID_VDEC_1] = &g12a_vdec_1.hw, 4678 + [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, 4679 + [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, 4680 + [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, 4681 + [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, 4682 + [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, 4683 + [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, 4684 + [CLKID_TS_DIV] = &g12a_ts_div.hw, 4685 + [CLKID_TS] = &g12a_ts.hw, 4686 + [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw, 4687 + [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw, 4688 + [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw, 4689 + [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw, 4690 + [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw, 4691 + [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw, 4692 + [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw, 4693 + [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw, 4694 + [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw, 4695 + [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw, 4696 + [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw, 4697 + [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw, 4698 + [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw, 4699 + [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw, 4700 + [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw, 4701 + [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw, 4702 + [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw, 4703 + [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw, 4704 + [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw, 4705 + [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw, 4706 + [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw, 4707 + [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw, 4708 + [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw, 4709 + [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw, 4710 + [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw, 4711 + [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw, 4712 + [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw, 4713 + [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw, 4714 + [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw, 4715 + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, 4716 + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, 4717 + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, 4718 + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, 4719 + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, 4720 + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, 4721 + [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw, 4722 + [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw, 4723 + [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw, 4724 + [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw, 4725 + [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw, 4726 + [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw, 4727 + [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw, 4728 + [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, 4729 + [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, 4738 4730 }; 4739 4731 4740 - static struct clk_hw_onecell_data sm1_hw_onecell_data = { 4741 - .hws = { 4742 - [CLKID_SYS_PLL] = &g12a_sys_pll.hw, 4743 - [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw, 4744 - [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw, 4745 - [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw, 4746 - [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw, 4747 - [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw, 4748 - [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, 4749 - [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, 4750 - [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, 4751 - [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, 4752 - [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, 4753 - [CLKID_CLK81] = &g12a_clk81.hw, 4754 - [CLKID_MPLL0] = &g12a_mpll0.hw, 4755 - [CLKID_MPLL1] = &g12a_mpll1.hw, 4756 - [CLKID_MPLL2] = &g12a_mpll2.hw, 4757 - [CLKID_MPLL3] = &g12a_mpll3.hw, 4758 - [CLKID_DDR] = &g12a_ddr.hw, 4759 - [CLKID_DOS] = &g12a_dos.hw, 4760 - [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw, 4761 - [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw, 4762 - [CLKID_ETH_PHY] = &g12a_eth_phy.hw, 4763 - [CLKID_ISA] = &g12a_isa.hw, 4764 - [CLKID_PL301] = &g12a_pl301.hw, 4765 - [CLKID_PERIPHS] = &g12a_periphs.hw, 4766 - [CLKID_SPICC0] = &g12a_spicc_0.hw, 4767 - [CLKID_I2C] = &g12a_i2c.hw, 4768 - [CLKID_SANA] = &g12a_sana.hw, 4769 - [CLKID_SD] = &g12a_sd.hw, 4770 - [CLKID_RNG0] = &g12a_rng0.hw, 4771 - [CLKID_UART0] = &g12a_uart0.hw, 4772 - [CLKID_SPICC1] = &g12a_spicc_1.hw, 4773 - [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw, 4774 - [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw, 4775 - [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw, 4776 - [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw, 4777 - [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw, 4778 - [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw, 4779 - [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw, 4780 - [CLKID_AUDIO] = &g12a_audio.hw, 4781 - [CLKID_ETH] = &g12a_eth_core.hw, 4782 - [CLKID_DEMUX] = &g12a_demux.hw, 4783 - [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw, 4784 - [CLKID_ADC] = &g12a_adc.hw, 4785 - [CLKID_UART1] = &g12a_uart1.hw, 4786 - [CLKID_G2D] = &g12a_g2d.hw, 4787 - [CLKID_RESET] = &g12a_reset.hw, 4788 - [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw, 4789 - [CLKID_PARSER] = &g12a_parser.hw, 4790 - [CLKID_USB] = &g12a_usb_general.hw, 4791 - [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw, 4792 - [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw, 4793 - [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw, 4794 - [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw, 4795 - [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw, 4796 - [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw, 4797 - [CLKID_BT656] = &g12a_bt656.hw, 4798 - [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw, 4799 - [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw, 4800 - [CLKID_UART2] = &g12a_uart2.hw, 4801 - [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, 4802 - [CLKID_GIC] = &g12a_gic.hw, 4803 - [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, 4804 - [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, 4805 - [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, 4806 - [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, 4807 - [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, 4808 - [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, 4809 - [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, 4810 - [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, 4811 - [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, 4812 - [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, 4813 - [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, 4814 - [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, 4815 - [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, 4816 - [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, 4817 - [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, 4818 - [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, 4819 - [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, 4820 - [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, 4821 - [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, 4822 - [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, 4823 - [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, 4824 - [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, 4825 - [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw, 4826 - [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw, 4827 - [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw, 4828 - [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw, 4829 - [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw, 4830 - [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw, 4831 - [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw, 4832 - [CLKID_DAC_CLK] = &g12a_dac_clk.hw, 4833 - [CLKID_AOCLK] = &g12a_aoclk_gate.hw, 4834 - [CLKID_IEC958] = &g12a_iec958_gate.hw, 4835 - [CLKID_ENC480P] = &g12a_enc480p.hw, 4836 - [CLKID_RNG1] = &g12a_rng1.hw, 4837 - [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw, 4838 - [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw, 4839 - [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, 4840 - [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, 4841 - [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, 4842 - [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, 4843 - [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, 4844 - [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, 4845 - [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, 4846 - [CLKID_DMA] = &g12a_dma.hw, 4847 - [CLKID_EFUSE] = &g12a_efuse.hw, 4848 - [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, 4849 - [CLKID_RESET_SEC] = &g12a_reset_sec.hw, 4850 - [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, 4851 - [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, 4852 - [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, 4853 - [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, 4854 - [CLKID_VPU_0] = &g12a_vpu_0.hw, 4855 - [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, 4856 - [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, 4857 - [CLKID_VPU_1] = &g12a_vpu_1.hw, 4858 - [CLKID_VPU] = &g12a_vpu.hw, 4859 - [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, 4860 - [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, 4861 - [CLKID_VAPB_0] = &g12a_vapb_0.hw, 4862 - [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, 4863 - [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, 4864 - [CLKID_VAPB_1] = &g12a_vapb_1.hw, 4865 - [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, 4866 - [CLKID_VAPB] = &g12a_vapb.hw, 4867 - [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, 4868 - [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, 4869 - [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, 4870 - [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, 4871 - [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, 4872 - [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, 4873 - [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, 4874 - [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, 4875 - [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, 4876 - [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, 4877 - [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, 4878 - [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, 4879 - [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, 4880 - [CLKID_VCLK] = &g12a_vclk.hw, 4881 - [CLKID_VCLK2] = &g12a_vclk2.hw, 4882 - [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, 4883 - [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, 4884 - [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, 4885 - [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, 4886 - [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, 4887 - [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, 4888 - [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, 4889 - [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, 4890 - [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, 4891 - [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, 4892 - [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, 4893 - [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, 4894 - [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, 4895 - [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw, 4896 - [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw, 4897 - [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, 4898 - [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, 4899 - [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, 4900 - [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, 4901 - [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, 4902 - [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, 4903 - [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, 4904 - [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, 4905 - [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, 4906 - [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, 4907 - [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, 4908 - [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, 4909 - [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, 4910 - [CLKID_HDMI] = &g12a_hdmi.hw, 4911 - [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, 4912 - [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, 4913 - [CLKID_MALI_0] = &g12a_mali_0.hw, 4914 - [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, 4915 - [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, 4916 - [CLKID_MALI_1] = &g12a_mali_1.hw, 4917 - [CLKID_MALI] = &g12a_mali.hw, 4918 - [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, 4919 - [CLKID_MPLL_50M] = &g12a_mpll_50m.hw, 4920 - [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, 4921 - [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, 4922 - [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, 4923 - [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, 4924 - [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, 4925 - [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, 4926 - [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, 4927 - [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, 4928 - [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, 4929 - [CLKID_CPU_CLK] = &g12a_cpu_clk.hw, 4930 - [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, 4931 - [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, 4932 - [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, 4933 - [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, 4934 - [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, 4935 - [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, 4936 - [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, 4937 - [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, 4938 - [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, 4939 - [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, 4940 - [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, 4941 - [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, 4942 - [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, 4943 - [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, 4944 - [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, 4945 - [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, 4946 - [CLKID_VDEC_1] = &g12a_vdec_1.hw, 4947 - [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, 4948 - [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, 4949 - [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, 4950 - [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, 4951 - [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, 4952 - [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, 4953 - [CLKID_TS_DIV] = &g12a_ts_div.hw, 4954 - [CLKID_TS] = &g12a_ts.hw, 4955 - [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw, 4956 - [CLKID_GP1_PLL] = &sm1_gp1_pll.hw, 4957 - [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw, 4958 - [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw, 4959 - [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw, 4960 - [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw, 4961 - [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw, 4962 - [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw, 4963 - [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw, 4964 - [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw, 4965 - [CLKID_DSU_CLK] = &sm1_dsu_clk.hw, 4966 - [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw, 4967 - [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw, 4968 - [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw, 4969 - [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, 4970 - [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, 4971 - [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, 4972 - [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, 4973 - [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, 4974 - [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, 4975 - [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw, 4976 - [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw, 4977 - [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw, 4978 - [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw, 4979 - [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw, 4980 - [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw, 4981 - [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw, 4982 - [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, 4983 - [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, 4984 - [NR_CLKS] = NULL, 4985 - }, 4986 - .num = NR_CLKS, 4732 + static struct clk_hw *sm1_hw_clks[] = { 4733 + [CLKID_SYS_PLL] = &g12a_sys_pll.hw, 4734 + [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw, 4735 + [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw, 4736 + [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw, 4737 + [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw, 4738 + [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw, 4739 + [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, 4740 + [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, 4741 + [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, 4742 + [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, 4743 + [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, 4744 + [CLKID_CLK81] = &g12a_clk81.hw, 4745 + [CLKID_MPLL0] = &g12a_mpll0.hw, 4746 + [CLKID_MPLL1] = &g12a_mpll1.hw, 4747 + [CLKID_MPLL2] = &g12a_mpll2.hw, 4748 + [CLKID_MPLL3] = &g12a_mpll3.hw, 4749 + [CLKID_DDR] = &g12a_ddr.hw, 4750 + [CLKID_DOS] = &g12a_dos.hw, 4751 + [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw, 4752 + [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw, 4753 + [CLKID_ETH_PHY] = &g12a_eth_phy.hw, 4754 + [CLKID_ISA] = &g12a_isa.hw, 4755 + [CLKID_PL301] = &g12a_pl301.hw, 4756 + [CLKID_PERIPHS] = &g12a_periphs.hw, 4757 + [CLKID_SPICC0] = &g12a_spicc_0.hw, 4758 + [CLKID_I2C] = &g12a_i2c.hw, 4759 + [CLKID_SANA] = &g12a_sana.hw, 4760 + [CLKID_SD] = &g12a_sd.hw, 4761 + [CLKID_RNG0] = &g12a_rng0.hw, 4762 + [CLKID_UART0] = &g12a_uart0.hw, 4763 + [CLKID_SPICC1] = &g12a_spicc_1.hw, 4764 + [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw, 4765 + [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw, 4766 + [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw, 4767 + [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw, 4768 + [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw, 4769 + [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw, 4770 + [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw, 4771 + [CLKID_AUDIO] = &g12a_audio.hw, 4772 + [CLKID_ETH] = &g12a_eth_core.hw, 4773 + [CLKID_DEMUX] = &g12a_demux.hw, 4774 + [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw, 4775 + [CLKID_ADC] = &g12a_adc.hw, 4776 + [CLKID_UART1] = &g12a_uart1.hw, 4777 + [CLKID_G2D] = &g12a_g2d.hw, 4778 + [CLKID_RESET] = &g12a_reset.hw, 4779 + [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw, 4780 + [CLKID_PARSER] = &g12a_parser.hw, 4781 + [CLKID_USB] = &g12a_usb_general.hw, 4782 + [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw, 4783 + [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw, 4784 + [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw, 4785 + [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw, 4786 + [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw, 4787 + [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw, 4788 + [CLKID_BT656] = &g12a_bt656.hw, 4789 + [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw, 4790 + [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw, 4791 + [CLKID_UART2] = &g12a_uart2.hw, 4792 + [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, 4793 + [CLKID_GIC] = &g12a_gic.hw, 4794 + [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, 4795 + [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, 4796 + [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, 4797 + [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, 4798 + [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, 4799 + [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, 4800 + [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, 4801 + [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, 4802 + [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, 4803 + [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, 4804 + [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, 4805 + [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, 4806 + [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, 4807 + [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, 4808 + [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, 4809 + [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, 4810 + [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, 4811 + [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, 4812 + [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, 4813 + [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, 4814 + [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, 4815 + [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, 4816 + [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw, 4817 + [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw, 4818 + [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw, 4819 + [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw, 4820 + [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw, 4821 + [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw, 4822 + [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw, 4823 + [CLKID_DAC_CLK] = &g12a_dac_clk.hw, 4824 + [CLKID_AOCLK] = &g12a_aoclk_gate.hw, 4825 + [CLKID_IEC958] = &g12a_iec958_gate.hw, 4826 + [CLKID_ENC480P] = &g12a_enc480p.hw, 4827 + [CLKID_RNG1] = &g12a_rng1.hw, 4828 + [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw, 4829 + [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw, 4830 + [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, 4831 + [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, 4832 + [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, 4833 + [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, 4834 + [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, 4835 + [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, 4836 + [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, 4837 + [CLKID_DMA] = &g12a_dma.hw, 4838 + [CLKID_EFUSE] = &g12a_efuse.hw, 4839 + [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, 4840 + [CLKID_RESET_SEC] = &g12a_reset_sec.hw, 4841 + [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, 4842 + [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, 4843 + [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, 4844 + [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, 4845 + [CLKID_VPU_0] = &g12a_vpu_0.hw, 4846 + [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, 4847 + [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, 4848 + [CLKID_VPU_1] = &g12a_vpu_1.hw, 4849 + [CLKID_VPU] = &g12a_vpu.hw, 4850 + [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, 4851 + [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, 4852 + [CLKID_VAPB_0] = &g12a_vapb_0.hw, 4853 + [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, 4854 + [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, 4855 + [CLKID_VAPB_1] = &g12a_vapb_1.hw, 4856 + [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, 4857 + [CLKID_VAPB] = &g12a_vapb.hw, 4858 + [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, 4859 + [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, 4860 + [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, 4861 + [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, 4862 + [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, 4863 + [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, 4864 + [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, 4865 + [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, 4866 + [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, 4867 + [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, 4868 + [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, 4869 + [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, 4870 + [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, 4871 + [CLKID_VCLK] = &g12a_vclk.hw, 4872 + [CLKID_VCLK2] = &g12a_vclk2.hw, 4873 + [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, 4874 + [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, 4875 + [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, 4876 + [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, 4877 + [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, 4878 + [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, 4879 + [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, 4880 + [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, 4881 + [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, 4882 + [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, 4883 + [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, 4884 + [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, 4885 + [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, 4886 + [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw, 4887 + [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw, 4888 + [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, 4889 + [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, 4890 + [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, 4891 + [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, 4892 + [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, 4893 + [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, 4894 + [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, 4895 + [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, 4896 + [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, 4897 + [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, 4898 + [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, 4899 + [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, 4900 + [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, 4901 + [CLKID_HDMI] = &g12a_hdmi.hw, 4902 + [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, 4903 + [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, 4904 + [CLKID_MALI_0] = &g12a_mali_0.hw, 4905 + [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, 4906 + [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, 4907 + [CLKID_MALI_1] = &g12a_mali_1.hw, 4908 + [CLKID_MALI] = &g12a_mali.hw, 4909 + [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, 4910 + [CLKID_MPLL_50M] = &g12a_mpll_50m.hw, 4911 + [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, 4912 + [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, 4913 + [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, 4914 + [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, 4915 + [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, 4916 + [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, 4917 + [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, 4918 + [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, 4919 + [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, 4920 + [CLKID_CPU_CLK] = &g12a_cpu_clk.hw, 4921 + [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, 4922 + [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, 4923 + [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, 4924 + [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, 4925 + [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, 4926 + [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, 4927 + [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, 4928 + [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, 4929 + [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, 4930 + [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, 4931 + [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, 4932 + [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, 4933 + [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, 4934 + [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, 4935 + [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, 4936 + [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, 4937 + [CLKID_VDEC_1] = &g12a_vdec_1.hw, 4938 + [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, 4939 + [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, 4940 + [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, 4941 + [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, 4942 + [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, 4943 + [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, 4944 + [CLKID_TS_DIV] = &g12a_ts_div.hw, 4945 + [CLKID_TS] = &g12a_ts.hw, 4946 + [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw, 4947 + [CLKID_GP1_PLL] = &sm1_gp1_pll.hw, 4948 + [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw, 4949 + [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw, 4950 + [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw, 4951 + [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw, 4952 + [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw, 4953 + [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw, 4954 + [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw, 4955 + [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw, 4956 + [CLKID_DSU_CLK] = &sm1_dsu_clk.hw, 4957 + [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw, 4958 + [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw, 4959 + [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw, 4960 + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, 4961 + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, 4962 + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, 4963 + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, 4964 + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, 4965 + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, 4966 + [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw, 4967 + [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw, 4968 + [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw, 4969 + [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw, 4970 + [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw, 4971 + [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw, 4972 + [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw, 4973 + [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, 4974 + [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, 4987 4975 }; 4988 4976 4989 4977 /* Convenience table to populate regmap in .probe */ ··· 5262 5274 5263 5275 static int meson_g12b_dvfs_setup(struct platform_device *pdev) 5264 5276 { 5265 - struct clk_hw **hws = g12b_hw_onecell_data.hws; 5277 + struct clk_hw **hws = g12b_hw_clks; 5266 5278 struct device *dev = &pdev->dev; 5267 5279 struct clk *notifier_clk; 5268 5280 struct clk_hw *xtal; ··· 5339 5351 5340 5352 static int meson_g12a_dvfs_setup(struct platform_device *pdev) 5341 5353 { 5342 - struct clk_hw **hws = g12a_hw_onecell_data.hws; 5354 + struct clk_hw **hws = g12a_hw_clks; 5343 5355 struct device *dev = &pdev->dev; 5344 5356 struct clk *notifier_clk; 5345 5357 int ret; ··· 5401 5413 .eeclkc_data = { 5402 5414 .regmap_clks = g12a_clk_regmaps, 5403 5415 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), 5404 - .hw_onecell_data = &g12a_hw_onecell_data, 5416 + .hw_clks = { 5417 + .hws = g12a_hw_clks, 5418 + .num = ARRAY_SIZE(g12a_hw_clks), 5419 + }, 5405 5420 .init_regs = g12a_init_regs, 5406 5421 .init_count = ARRAY_SIZE(g12a_init_regs), 5407 5422 }, ··· 5415 5424 .eeclkc_data = { 5416 5425 .regmap_clks = g12a_clk_regmaps, 5417 5426 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), 5418 - .hw_onecell_data = &g12b_hw_onecell_data, 5427 + .hw_clks = { 5428 + .hws = g12b_hw_clks, 5429 + .num = ARRAY_SIZE(g12b_hw_clks), 5430 + }, 5419 5431 }, 5420 5432 .dvfs_setup = meson_g12b_dvfs_setup, 5421 5433 }; ··· 5427 5433 .eeclkc_data = { 5428 5434 .regmap_clks = g12a_clk_regmaps, 5429 5435 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), 5430 - .hw_onecell_data = &sm1_hw_onecell_data, 5436 + .hw_clks = { 5437 + .hws = sm1_hw_clks, 5438 + .num = ARRAY_SIZE(sm1_hw_clks), 5439 + }, 5431 5440 }, 5432 5441 .dvfs_setup = meson_g12a_dvfs_setup, 5433 5442 };
-2
drivers/clk/meson/g12a.h
··· 266 266 #define CLKID_NNA_CORE_CLK_DIV 266 267 267 #define CLKID_MIPI_DSI_PXCLK_DIV 268 268 268 269 - #define NR_CLKS 271 270 - 271 269 /* include the CLKIDs that have been made part of the DT binding */ 272 270 #include <dt-bindings/clock/g12a-clkc.h> 273 271
+420 -422
drivers/clk/meson/gxbb.c
··· 2728 2728 2729 2729 /* Array of all clocks provided by this provider */ 2730 2730 2731 - static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 2732 - .hws = { 2733 - [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2734 - [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 2735 - [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2736 - [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2737 - [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2738 - [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2739 - [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2740 - [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2741 - [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2742 - [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 2743 - [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 2744 - [CLKID_CLK81] = &gxbb_clk81.hw, 2745 - [CLKID_MPLL0] = &gxbb_mpll0.hw, 2746 - [CLKID_MPLL1] = &gxbb_mpll1.hw, 2747 - [CLKID_MPLL2] = &gxbb_mpll2.hw, 2748 - [CLKID_DDR] = &gxbb_ddr.hw, 2749 - [CLKID_DOS] = &gxbb_dos.hw, 2750 - [CLKID_ISA] = &gxbb_isa.hw, 2751 - [CLKID_PL301] = &gxbb_pl301.hw, 2752 - [CLKID_PERIPHS] = &gxbb_periphs.hw, 2753 - [CLKID_SPICC] = &gxbb_spicc.hw, 2754 - [CLKID_I2C] = &gxbb_i2c.hw, 2755 - [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2756 - [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2757 - [CLKID_RNG0] = &gxbb_rng0.hw, 2758 - [CLKID_UART0] = &gxbb_uart0.hw, 2759 - [CLKID_SDHC] = &gxbb_sdhc.hw, 2760 - [CLKID_STREAM] = &gxbb_stream.hw, 2761 - [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2762 - [CLKID_SDIO] = &gxbb_sdio.hw, 2763 - [CLKID_ABUF] = &gxbb_abuf.hw, 2764 - [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2765 - [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2766 - [CLKID_SPI] = &gxbb_spi.hw, 2767 - [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2768 - [CLKID_ETH] = &gxbb_eth.hw, 2769 - [CLKID_DEMUX] = &gxbb_demux.hw, 2770 - [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2771 - [CLKID_IEC958] = &gxbb_iec958.hw, 2772 - [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2773 - [CLKID_AMCLK] = &gxbb_amclk.hw, 2774 - [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2775 - [CLKID_MIXER] = &gxbb_mixer.hw, 2776 - [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2777 - [CLKID_ADC] = &gxbb_adc.hw, 2778 - [CLKID_BLKMV] = &gxbb_blkmv.hw, 2779 - [CLKID_AIU] = &gxbb_aiu.hw, 2780 - [CLKID_UART1] = &gxbb_uart1.hw, 2781 - [CLKID_G2D] = &gxbb_g2d.hw, 2782 - [CLKID_USB0] = &gxbb_usb0.hw, 2783 - [CLKID_USB1] = &gxbb_usb1.hw, 2784 - [CLKID_RESET] = &gxbb_reset.hw, 2785 - [CLKID_NAND] = &gxbb_nand.hw, 2786 - [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2787 - [CLKID_USB] = &gxbb_usb.hw, 2788 - [CLKID_VDIN1] = &gxbb_vdin1.hw, 2789 - [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2790 - [CLKID_EFUSE] = &gxbb_efuse.hw, 2791 - [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2792 - [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2793 - [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2794 - [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2795 - [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2796 - [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2797 - [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2798 - [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2799 - [CLKID_DVIN] = &gxbb_dvin.hw, 2800 - [CLKID_UART2] = &gxbb_uart2.hw, 2801 - [CLKID_SANA] = &gxbb_sana.hw, 2802 - [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2803 - [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2804 - [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2805 - [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2806 - [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2807 - [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2808 - [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2809 - [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2810 - [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2811 - [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2812 - [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2813 - [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2814 - [CLKID_ENC480P] = &gxbb_enc480p.hw, 2815 - [CLKID_RNG1] = &gxbb_rng1.hw, 2816 - [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2817 - [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2818 - [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2819 - [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2820 - [CLKID_EDP] = &gxbb_edp.hw, 2821 - [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2822 - [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2823 - [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2824 - [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2825 - [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 2826 - [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 2827 - [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 2828 - [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 2829 - [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 2830 - [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 2831 - [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2832 - [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2833 - [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2834 - [CLKID_MALI_0] = &gxbb_mali_0.hw, 2835 - [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2836 - [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2837 - [CLKID_MALI_1] = &gxbb_mali_1.hw, 2838 - [CLKID_MALI] = &gxbb_mali.hw, 2839 - [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 2840 - [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 2841 - [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 2842 - [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 2843 - [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 2844 - [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 2845 - [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 2846 - [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2847 - [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2848 - [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2849 - [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2850 - [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2851 - [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2852 - [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2853 - [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2854 - [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2855 - [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2856 - [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2857 - [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2858 - [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2859 - [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2860 - [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2861 - [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2862 - [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2863 - [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2864 - [CLKID_VPU] = &gxbb_vpu.hw, 2865 - [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2866 - [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2867 - [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2868 - [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2869 - [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2870 - [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2871 - [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2872 - [CLKID_VAPB] = &gxbb_vapb.hw, 2873 - [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 2874 - [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2875 - [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2876 - [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2877 - [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2878 - [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2879 - [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2880 - [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2881 - [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2882 - [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2883 - [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2884 - [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2885 - [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2886 - [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2887 - [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2888 - [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 2889 - [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 2890 - [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 2891 - [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 2892 - [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 2893 - [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 2894 - [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 2895 - [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 2896 - [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 2897 - [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 2898 - [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 2899 - [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 2900 - [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 2901 - [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 2902 - [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 2903 - [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 2904 - [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 2905 - [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 2906 - [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 2907 - [CLKID_VCLK] = &gxbb_vclk.hw, 2908 - [CLKID_VCLK2] = &gxbb_vclk2.hw, 2909 - [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 2910 - [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 2911 - [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 2912 - [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 2913 - [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 2914 - [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 2915 - [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 2916 - [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 2917 - [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 2918 - [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 2919 - [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 2920 - [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 2921 - [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 2922 - [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 2923 - [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 2924 - [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 2925 - [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 2926 - [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 2927 - [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 2928 - [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 2929 - [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 2930 - [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 2931 - [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 2932 - [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 2933 - [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 2934 - [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 2935 - [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 2936 - [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 2937 - [CLKID_HDMI] = &gxbb_hdmi.hw, 2938 - [NR_CLKS] = NULL, 2939 - }, 2940 - .num = NR_CLKS, 2731 + static struct clk_hw *gxbb_hw_clks[] = { 2732 + [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2733 + [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 2734 + [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2735 + [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2736 + [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2737 + [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2738 + [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2739 + [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2740 + [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2741 + [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 2742 + [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 2743 + [CLKID_CLK81] = &gxbb_clk81.hw, 2744 + [CLKID_MPLL0] = &gxbb_mpll0.hw, 2745 + [CLKID_MPLL1] = &gxbb_mpll1.hw, 2746 + [CLKID_MPLL2] = &gxbb_mpll2.hw, 2747 + [CLKID_DDR] = &gxbb_ddr.hw, 2748 + [CLKID_DOS] = &gxbb_dos.hw, 2749 + [CLKID_ISA] = &gxbb_isa.hw, 2750 + [CLKID_PL301] = &gxbb_pl301.hw, 2751 + [CLKID_PERIPHS] = &gxbb_periphs.hw, 2752 + [CLKID_SPICC] = &gxbb_spicc.hw, 2753 + [CLKID_I2C] = &gxbb_i2c.hw, 2754 + [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2755 + [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2756 + [CLKID_RNG0] = &gxbb_rng0.hw, 2757 + [CLKID_UART0] = &gxbb_uart0.hw, 2758 + [CLKID_SDHC] = &gxbb_sdhc.hw, 2759 + [CLKID_STREAM] = &gxbb_stream.hw, 2760 + [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2761 + [CLKID_SDIO] = &gxbb_sdio.hw, 2762 + [CLKID_ABUF] = &gxbb_abuf.hw, 2763 + [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2764 + [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2765 + [CLKID_SPI] = &gxbb_spi.hw, 2766 + [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2767 + [CLKID_ETH] = &gxbb_eth.hw, 2768 + [CLKID_DEMUX] = &gxbb_demux.hw, 2769 + [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2770 + [CLKID_IEC958] = &gxbb_iec958.hw, 2771 + [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2772 + [CLKID_AMCLK] = &gxbb_amclk.hw, 2773 + [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2774 + [CLKID_MIXER] = &gxbb_mixer.hw, 2775 + [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2776 + [CLKID_ADC] = &gxbb_adc.hw, 2777 + [CLKID_BLKMV] = &gxbb_blkmv.hw, 2778 + [CLKID_AIU] = &gxbb_aiu.hw, 2779 + [CLKID_UART1] = &gxbb_uart1.hw, 2780 + [CLKID_G2D] = &gxbb_g2d.hw, 2781 + [CLKID_USB0] = &gxbb_usb0.hw, 2782 + [CLKID_USB1] = &gxbb_usb1.hw, 2783 + [CLKID_RESET] = &gxbb_reset.hw, 2784 + [CLKID_NAND] = &gxbb_nand.hw, 2785 + [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2786 + [CLKID_USB] = &gxbb_usb.hw, 2787 + [CLKID_VDIN1] = &gxbb_vdin1.hw, 2788 + [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2789 + [CLKID_EFUSE] = &gxbb_efuse.hw, 2790 + [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2791 + [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2792 + [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2793 + [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2794 + [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2795 + [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2796 + [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2797 + [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2798 + [CLKID_DVIN] = &gxbb_dvin.hw, 2799 + [CLKID_UART2] = &gxbb_uart2.hw, 2800 + [CLKID_SANA] = &gxbb_sana.hw, 2801 + [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2802 + [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2803 + [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2804 + [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2805 + [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2806 + [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2807 + [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2808 + [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2809 + [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2810 + [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2811 + [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2812 + [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2813 + [CLKID_ENC480P] = &gxbb_enc480p.hw, 2814 + [CLKID_RNG1] = &gxbb_rng1.hw, 2815 + [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2816 + [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2817 + [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2818 + [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2819 + [CLKID_EDP] = &gxbb_edp.hw, 2820 + [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2821 + [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2822 + [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2823 + [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2824 + [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 2825 + [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 2826 + [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 2827 + [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 2828 + [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 2829 + [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 2830 + [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2831 + [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2832 + [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2833 + [CLKID_MALI_0] = &gxbb_mali_0.hw, 2834 + [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2835 + [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2836 + [CLKID_MALI_1] = &gxbb_mali_1.hw, 2837 + [CLKID_MALI] = &gxbb_mali.hw, 2838 + [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 2839 + [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 2840 + [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 2841 + [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 2842 + [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 2843 + [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 2844 + [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 2845 + [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2846 + [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2847 + [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2848 + [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2849 + [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2850 + [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2851 + [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2852 + [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2853 + [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2854 + [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2855 + [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2856 + [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2857 + [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2858 + [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2859 + [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2860 + [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2861 + [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2862 + [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2863 + [CLKID_VPU] = &gxbb_vpu.hw, 2864 + [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2865 + [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2866 + [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2867 + [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2868 + [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2869 + [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2870 + [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2871 + [CLKID_VAPB] = &gxbb_vapb.hw, 2872 + [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 2873 + [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2874 + [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2875 + [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2876 + [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2877 + [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2878 + [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2879 + [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2880 + [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2881 + [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2882 + [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2883 + [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2884 + [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2885 + [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2886 + [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2887 + [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 2888 + [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 2889 + [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 2890 + [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 2891 + [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 2892 + [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 2893 + [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 2894 + [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 2895 + [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 2896 + [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 2897 + [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 2898 + [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 2899 + [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 2900 + [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 2901 + [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 2902 + [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 2903 + [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 2904 + [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 2905 + [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 2906 + [CLKID_VCLK] = &gxbb_vclk.hw, 2907 + [CLKID_VCLK2] = &gxbb_vclk2.hw, 2908 + [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 2909 + [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 2910 + [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 2911 + [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 2912 + [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 2913 + [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 2914 + [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 2915 + [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 2916 + [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 2917 + [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 2918 + [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 2919 + [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 2920 + [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 2921 + [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 2922 + [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 2923 + [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 2924 + [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 2925 + [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 2926 + [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 2927 + [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 2928 + [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 2929 + [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 2930 + [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 2931 + [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 2932 + [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 2933 + [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 2934 + [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 2935 + [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 2936 + [CLKID_HDMI] = &gxbb_hdmi.hw, 2941 2937 }; 2942 2938 2943 - static struct clk_hw_onecell_data gxl_hw_onecell_data = { 2944 - .hws = { 2945 - [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2946 - [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 2947 - [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2948 - [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2949 - [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2950 - [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2951 - [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2952 - [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2953 - [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2954 - [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 2955 - [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 2956 - [CLKID_CLK81] = &gxbb_clk81.hw, 2957 - [CLKID_MPLL0] = &gxbb_mpll0.hw, 2958 - [CLKID_MPLL1] = &gxbb_mpll1.hw, 2959 - [CLKID_MPLL2] = &gxbb_mpll2.hw, 2960 - [CLKID_DDR] = &gxbb_ddr.hw, 2961 - [CLKID_DOS] = &gxbb_dos.hw, 2962 - [CLKID_ISA] = &gxbb_isa.hw, 2963 - [CLKID_PL301] = &gxbb_pl301.hw, 2964 - [CLKID_PERIPHS] = &gxbb_periphs.hw, 2965 - [CLKID_SPICC] = &gxbb_spicc.hw, 2966 - [CLKID_I2C] = &gxbb_i2c.hw, 2967 - [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2968 - [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2969 - [CLKID_RNG0] = &gxbb_rng0.hw, 2970 - [CLKID_UART0] = &gxbb_uart0.hw, 2971 - [CLKID_SDHC] = &gxbb_sdhc.hw, 2972 - [CLKID_STREAM] = &gxbb_stream.hw, 2973 - [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2974 - [CLKID_SDIO] = &gxbb_sdio.hw, 2975 - [CLKID_ABUF] = &gxbb_abuf.hw, 2976 - [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2977 - [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2978 - [CLKID_SPI] = &gxbb_spi.hw, 2979 - [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2980 - [CLKID_ETH] = &gxbb_eth.hw, 2981 - [CLKID_DEMUX] = &gxbb_demux.hw, 2982 - [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2983 - [CLKID_IEC958] = &gxbb_iec958.hw, 2984 - [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2985 - [CLKID_AMCLK] = &gxbb_amclk.hw, 2986 - [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2987 - [CLKID_MIXER] = &gxbb_mixer.hw, 2988 - [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2989 - [CLKID_ADC] = &gxbb_adc.hw, 2990 - [CLKID_BLKMV] = &gxbb_blkmv.hw, 2991 - [CLKID_AIU] = &gxbb_aiu.hw, 2992 - [CLKID_UART1] = &gxbb_uart1.hw, 2993 - [CLKID_G2D] = &gxbb_g2d.hw, 2994 - [CLKID_USB0] = &gxbb_usb0.hw, 2995 - [CLKID_USB1] = &gxbb_usb1.hw, 2996 - [CLKID_RESET] = &gxbb_reset.hw, 2997 - [CLKID_NAND] = &gxbb_nand.hw, 2998 - [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2999 - [CLKID_USB] = &gxbb_usb.hw, 3000 - [CLKID_VDIN1] = &gxbb_vdin1.hw, 3001 - [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 3002 - [CLKID_EFUSE] = &gxbb_efuse.hw, 3003 - [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 3004 - [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 3005 - [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 3006 - [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 3007 - [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 3008 - [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 3009 - [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 3010 - [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 3011 - [CLKID_DVIN] = &gxbb_dvin.hw, 3012 - [CLKID_UART2] = &gxbb_uart2.hw, 3013 - [CLKID_SANA] = &gxbb_sana.hw, 3014 - [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 3015 - [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 3016 - [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 3017 - [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 3018 - [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 3019 - [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 3020 - [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 3021 - [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 3022 - [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 3023 - [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 3024 - [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 3025 - [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 3026 - [CLKID_ENC480P] = &gxbb_enc480p.hw, 3027 - [CLKID_RNG1] = &gxbb_rng1.hw, 3028 - [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 3029 - [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 3030 - [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 3031 - [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 3032 - [CLKID_EDP] = &gxbb_edp.hw, 3033 - [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 3034 - [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 3035 - [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 3036 - [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 3037 - [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 3038 - [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 3039 - [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 3040 - [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 3041 - [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 3042 - [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 3043 - [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 3044 - [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 3045 - [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 3046 - [CLKID_MALI_0] = &gxbb_mali_0.hw, 3047 - [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 3048 - [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 3049 - [CLKID_MALI_1] = &gxbb_mali_1.hw, 3050 - [CLKID_MALI] = &gxbb_mali.hw, 3051 - [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 3052 - [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 3053 - [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 3054 - [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 3055 - [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 3056 - [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 3057 - [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 3058 - [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 3059 - [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 3060 - [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 3061 - [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 3062 - [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 3063 - [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 3064 - [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 3065 - [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 3066 - [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 3067 - [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 3068 - [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 3069 - [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 3070 - [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 3071 - [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 3072 - [CLKID_VPU_0] = &gxbb_vpu_0.hw, 3073 - [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 3074 - [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 3075 - [CLKID_VPU_1] = &gxbb_vpu_1.hw, 3076 - [CLKID_VPU] = &gxbb_vpu.hw, 3077 - [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 3078 - [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 3079 - [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 3080 - [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 3081 - [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 3082 - [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 3083 - [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 3084 - [CLKID_VAPB] = &gxbb_vapb.hw, 3085 - [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw, 3086 - [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 3087 - [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 3088 - [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 3089 - [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 3090 - [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 3091 - [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 3092 - [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 3093 - [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3094 - [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3095 - [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3096 - [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3097 - [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3098 - [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3099 - [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 3100 - [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 3101 - [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 3102 - [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 3103 - [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 3104 - [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw, 3105 - [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 3106 - [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 3107 - [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 3108 - [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 3109 - [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3110 - [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3111 - [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3112 - [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3113 - [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3114 - [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3115 - [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3116 - [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3117 - [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3118 - [CLKID_VCLK] = &gxbb_vclk.hw, 3119 - [CLKID_VCLK2] = &gxbb_vclk2.hw, 3120 - [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3121 - [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3122 - [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3123 - [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3124 - [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3125 - [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3126 - [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3127 - [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3128 - [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3129 - [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3130 - [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3131 - [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3132 - [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3133 - [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3134 - [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3135 - [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3136 - [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3137 - [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3138 - [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3139 - [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3140 - [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3141 - [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3142 - [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3143 - [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3144 - [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3145 - [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3146 - [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3147 - [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3148 - [CLKID_HDMI] = &gxbb_hdmi.hw, 3149 - [CLKID_ACODEC] = &gxl_acodec.hw, 3150 - [NR_CLKS] = NULL, 3151 - }, 3152 - .num = NR_CLKS, 2939 + static struct clk_hw *gxl_hw_clks[] = { 2940 + [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2941 + [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 2942 + [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2943 + [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2944 + [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2945 + [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2946 + [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2947 + [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2948 + [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2949 + [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 2950 + [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 2951 + [CLKID_CLK81] = &gxbb_clk81.hw, 2952 + [CLKID_MPLL0] = &gxbb_mpll0.hw, 2953 + [CLKID_MPLL1] = &gxbb_mpll1.hw, 2954 + [CLKID_MPLL2] = &gxbb_mpll2.hw, 2955 + [CLKID_DDR] = &gxbb_ddr.hw, 2956 + [CLKID_DOS] = &gxbb_dos.hw, 2957 + [CLKID_ISA] = &gxbb_isa.hw, 2958 + [CLKID_PL301] = &gxbb_pl301.hw, 2959 + [CLKID_PERIPHS] = &gxbb_periphs.hw, 2960 + [CLKID_SPICC] = &gxbb_spicc.hw, 2961 + [CLKID_I2C] = &gxbb_i2c.hw, 2962 + [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2963 + [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2964 + [CLKID_RNG0] = &gxbb_rng0.hw, 2965 + [CLKID_UART0] = &gxbb_uart0.hw, 2966 + [CLKID_SDHC] = &gxbb_sdhc.hw, 2967 + [CLKID_STREAM] = &gxbb_stream.hw, 2968 + [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2969 + [CLKID_SDIO] = &gxbb_sdio.hw, 2970 + [CLKID_ABUF] = &gxbb_abuf.hw, 2971 + [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2972 + [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2973 + [CLKID_SPI] = &gxbb_spi.hw, 2974 + [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2975 + [CLKID_ETH] = &gxbb_eth.hw, 2976 + [CLKID_DEMUX] = &gxbb_demux.hw, 2977 + [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2978 + [CLKID_IEC958] = &gxbb_iec958.hw, 2979 + [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2980 + [CLKID_AMCLK] = &gxbb_amclk.hw, 2981 + [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2982 + [CLKID_MIXER] = &gxbb_mixer.hw, 2983 + [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2984 + [CLKID_ADC] = &gxbb_adc.hw, 2985 + [CLKID_BLKMV] = &gxbb_blkmv.hw, 2986 + [CLKID_AIU] = &gxbb_aiu.hw, 2987 + [CLKID_UART1] = &gxbb_uart1.hw, 2988 + [CLKID_G2D] = &gxbb_g2d.hw, 2989 + [CLKID_USB0] = &gxbb_usb0.hw, 2990 + [CLKID_USB1] = &gxbb_usb1.hw, 2991 + [CLKID_RESET] = &gxbb_reset.hw, 2992 + [CLKID_NAND] = &gxbb_nand.hw, 2993 + [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2994 + [CLKID_USB] = &gxbb_usb.hw, 2995 + [CLKID_VDIN1] = &gxbb_vdin1.hw, 2996 + [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2997 + [CLKID_EFUSE] = &gxbb_efuse.hw, 2998 + [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2999 + [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 3000 + [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 3001 + [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 3002 + [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 3003 + [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 3004 + [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 3005 + [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 3006 + [CLKID_DVIN] = &gxbb_dvin.hw, 3007 + [CLKID_UART2] = &gxbb_uart2.hw, 3008 + [CLKID_SANA] = &gxbb_sana.hw, 3009 + [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 3010 + [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 3011 + [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 3012 + [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 3013 + [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 3014 + [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 3015 + [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 3016 + [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 3017 + [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 3018 + [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 3019 + [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 3020 + [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 3021 + [CLKID_ENC480P] = &gxbb_enc480p.hw, 3022 + [CLKID_RNG1] = &gxbb_rng1.hw, 3023 + [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 3024 + [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 3025 + [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 3026 + [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 3027 + [CLKID_EDP] = &gxbb_edp.hw, 3028 + [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 3029 + [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 3030 + [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 3031 + [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 3032 + [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 3033 + [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 3034 + [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 3035 + [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 3036 + [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 3037 + [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 3038 + [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 3039 + [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 3040 + [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 3041 + [CLKID_MALI_0] = &gxbb_mali_0.hw, 3042 + [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 3043 + [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 3044 + [CLKID_MALI_1] = &gxbb_mali_1.hw, 3045 + [CLKID_MALI] = &gxbb_mali.hw, 3046 + [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 3047 + [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 3048 + [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 3049 + [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 3050 + [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 3051 + [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 3052 + [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 3053 + [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 3054 + [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 3055 + [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 3056 + [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 3057 + [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 3058 + [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 3059 + [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 3060 + [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 3061 + [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 3062 + [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 3063 + [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 3064 + [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 3065 + [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 3066 + [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 3067 + [CLKID_VPU_0] = &gxbb_vpu_0.hw, 3068 + [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 3069 + [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 3070 + [CLKID_VPU_1] = &gxbb_vpu_1.hw, 3071 + [CLKID_VPU] = &gxbb_vpu.hw, 3072 + [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 3073 + [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 3074 + [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 3075 + [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 3076 + [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 3077 + [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 3078 + [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 3079 + [CLKID_VAPB] = &gxbb_vapb.hw, 3080 + [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw, 3081 + [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 3082 + [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 3083 + [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 3084 + [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 3085 + [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 3086 + [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 3087 + [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 3088 + [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3089 + [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3090 + [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3091 + [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3092 + [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3093 + [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3094 + [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 3095 + [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 3096 + [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 3097 + [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 3098 + [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 3099 + [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw, 3100 + [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 3101 + [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 3102 + [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 3103 + [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 3104 + [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3105 + [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3106 + [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3107 + [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3108 + [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3109 + [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3110 + [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3111 + [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3112 + [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3113 + [CLKID_VCLK] = &gxbb_vclk.hw, 3114 + [CLKID_VCLK2] = &gxbb_vclk2.hw, 3115 + [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3116 + [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3117 + [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3118 + [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3119 + [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3120 + [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3121 + [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3122 + [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3123 + [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3124 + [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3125 + [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3126 + [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3127 + [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3128 + [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3129 + [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3130 + [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3131 + [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3132 + [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3133 + [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3134 + [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3135 + [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3136 + [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3137 + [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3138 + [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3139 + [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3140 + [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3141 + [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3142 + [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3143 + [CLKID_HDMI] = &gxbb_hdmi.hw, 3144 + [CLKID_ACODEC] = &gxl_acodec.hw, 3153 3145 }; 3154 3146 3155 3147 static struct clk_regmap *const gxbb_clk_regmaps[] = { ··· 3536 3544 static const struct meson_eeclkc_data gxbb_clkc_data = { 3537 3545 .regmap_clks = gxbb_clk_regmaps, 3538 3546 .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps), 3539 - .hw_onecell_data = &gxbb_hw_onecell_data, 3547 + .hw_clks = { 3548 + .hws = gxbb_hw_clks, 3549 + .num = ARRAY_SIZE(gxbb_hw_clks), 3550 + }, 3540 3551 }; 3541 3552 3542 3553 static const struct meson_eeclkc_data gxl_clkc_data = { 3543 3554 .regmap_clks = gxl_clk_regmaps, 3544 3555 .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps), 3545 - .hw_onecell_data = &gxl_hw_onecell_data, 3556 + .hw_clks = { 3557 + .hws = gxl_hw_clks, 3558 + .num = ARRAY_SIZE(gxl_hw_clks), 3559 + }, 3546 3560 }; 3547 3561 3548 3562 static const struct of_device_id clkc_match_table[] = {
-2
drivers/clk/meson/gxbb.h
··· 188 188 #define CLKID_HDMI_SEL 203 189 189 #define CLKID_HDMI_DIV 204 190 190 191 - #define NR_CLKS 207 192 - 193 191 /* include the CLKIDs that have been made part of the DT binding */ 194 192 #include <dt-bindings/clock/gxbb-clkc.h> 195 193
+4 -5
drivers/clk/meson/meson-eeclk.c
··· 43 43 for (i = 0; i < data->regmap_clk_num; i++) 44 44 data->regmap_clks[i]->map = map; 45 45 46 - for (i = 0; i < data->hw_onecell_data->num; i++) { 46 + for (i = 0; i < data->hw_clks.num; i++) { 47 47 /* array might be sparse */ 48 - if (!data->hw_onecell_data->hws[i]) 48 + if (!data->hw_clks.hws[i]) 49 49 continue; 50 50 51 - ret = devm_clk_hw_register(dev, data->hw_onecell_data->hws[i]); 51 + ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]); 52 52 if (ret) { 53 53 dev_err(dev, "Clock registration failed\n"); 54 54 return ret; 55 55 } 56 56 } 57 57 58 - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 59 - data->hw_onecell_data); 58 + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks); 60 59 } 61 60 EXPORT_SYMBOL_GPL(meson_eeclkc_probe); 62 61 MODULE_LICENSE("GPL v2");
+2 -1
drivers/clk/meson/meson-eeclk.h
··· 9 9 10 10 #include <linux/clk-provider.h> 11 11 #include "clk-regmap.h" 12 + #include "meson-clkc-utils.h" 12 13 13 14 struct platform_device; 14 15 ··· 18 17 unsigned int regmap_clk_num; 19 18 const struct reg_sequence *init_regs; 20 19 unsigned int init_count; 21 - struct clk_hw_onecell_data *hw_onecell_data; 20 + struct meson_clk_hw_data hw_clks; 22 21 }; 23 22 24 23 int meson_eeclkc_probe(struct platform_device *pdev);