tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20230208091340.124641-1-konrad.dybcio@linaro.org' into HEAD
Introduce SM6115 GPUCC devicetree bindings, to make it possible to use
clock defines in the devicetree source.
+285
+58
Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml
+58
Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+
%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Graphics Clock & Reset Controller on SM6115
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maintainers:
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- Konrad Dybcio <konrad.dybcio@linaro.org>
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description: |
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Qualcomm graphics clock control module provides clocks, resets and power
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domains on Qualcomm SoCs.
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+
16
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See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h
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properties:
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compatible:
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enum:
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- qcom,sm6115-gpucc
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+
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 main branch source
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- description: GPLL0 main div source
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required:
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- compatible
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- clocks
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm6115.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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+
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clock-controller@5990000 {
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compatible = "qcom,sm6115-gpucc";
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reg = <0x05990000 0x9000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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};
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+
...
+64
Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml
+64
Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+
%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Graphics Clock & Reset Controller on SM6125
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+
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maintainers:
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- Konrad Dybcio <konrad.dybcio@linaro.org>
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+
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description: |
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+
Qualcomm graphics clock control module provides clocks and power domains on
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+
Qualcomm SoCs.
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+
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+
See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
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+
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properties:
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compatible:
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+
enum:
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- qcom,sm6125-gpucc
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+
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clocks:
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items:
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+
- description: Board XO source
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- description: GPLL0 main branch source
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+
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'#clock-cells':
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const: 1
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+
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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+
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm6125.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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+
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soc {
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#address-cells = <1>;
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+
#size-cells = <1>;
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+
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clock-controller@5990000 {
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compatible = "qcom,sm6125-gpucc";
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reg = <0x05990000 0x9000>;
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+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_CLK_SRC>;
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#clock-cells = <1>;
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+
#power-domain-cells = <1>;
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};
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};
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+
...
+60
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
+60
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Graphics Clock & Reset Controller on SM6375
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+
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maintainers:
10
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- Konrad Dybcio <konrad.dybcio@linaro.org>
11
+
12
+
description: |
13
+
Qualcomm graphics clock control module provides clocks, resets and power
14
+
domains on Qualcomm SoCs.
15
+
16
+
See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
17
+
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properties:
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+
compatible:
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+
enum:
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+
- qcom,sm6375-gpucc
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+
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 main branch source
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+
- description: GPLL0 div branch source
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- description: SNoC DVM GFX source
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+
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required:
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- compatible
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- clocks
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+
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allOf:
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- $ref: qcom,gcc.yaml#
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+
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unevaluatedProperties: false
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+
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm6375-gcc.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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+
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clock-controller@5990000 {
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compatible = "qcom,sm6375-gpucc";
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reg = <0 0x05990000 0 0x9000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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};
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+
...
+36
include/dt-bindings/clock/qcom,sm6115-gpucc.h
+36
include/dt-bindings/clock/qcom,sm6115-gpucc.h
···
1
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H
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/* GPU_CC clocks */
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#define GPU_CC_PLL0 0
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#define GPU_CC_PLL0_OUT_AUX2 1
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#define GPU_CC_PLL1 2
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#define GPU_CC_PLL1_OUT_AUX 3
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#define GPU_CC_AHB_CLK 4
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#define GPU_CC_CRC_AHB_CLK 5
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#define GPU_CC_CX_GFX3D_CLK 6
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#define GPU_CC_CX_GMU_CLK 7
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#define GPU_CC_CX_SNOC_DVM_CLK 8
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#define GPU_CC_CXO_AON_CLK 9
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#define GPU_CC_CXO_CLK 10
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#define GPU_CC_GMU_CLK_SRC 11
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#define GPU_CC_GX_CXO_CLK 12
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#define GPU_CC_GX_GFX3D_CLK 13
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#define GPU_CC_GX_GFX3D_CLK_SRC 14
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#define GPU_CC_SLEEP_CLK 15
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
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+
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/* Resets */
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#define GPU_GX_BCR 0
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/* GDSCs */
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#define GPU_CX_GDSC 0
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#define GPU_GX_GDSC 1
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+
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#endif
+31
include/dt-bindings/clock/qcom,sm6125-gpucc.h
+31
include/dt-bindings/clock/qcom,sm6125-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
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/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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+
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H
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/* Clocks */
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#define GPU_CC_PLL0_OUT_AUX2 0
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#define GPU_CC_PLL1_OUT_AUX2 1
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#define GPU_CC_CRC_AHB_CLK 2
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#define GPU_CC_CX_APB_CLK 3
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#define GPU_CC_CX_GFX3D_CLK 4
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#define GPU_CC_CX_GMU_CLK 5
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#define GPU_CC_CX_SNOC_DVM_CLK 6
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#define GPU_CC_CXO_AON_CLK 7
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#define GPU_CC_CXO_CLK 8
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#define GPU_CC_GMU_CLK_SRC 9
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#define GPU_CC_SLEEP_CLK 10
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#define GPU_CC_GX_GFX3D_CLK 11
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#define GPU_CC_GX_GFX3D_CLK_SRC 12
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#define GPU_CC_AHB_CLK 13
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
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+
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+
/* GDSCs */
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+
#define GPU_CX_GDSC 0
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#define GPU_GX_GDSC 1
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+
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+
#endif
+36
include/dt-bindings/clock/qcom,sm6375-gpucc.h
+36
include/dt-bindings/clock/qcom,sm6375-gpucc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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+
*/
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+
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H
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+
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/* GPU CC clocks */
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#define GPU_CC_PLL0 0
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#define GPU_CC_PLL1 1
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#define GPU_CC_AHB_CLK 2
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#define GPU_CC_CX_GFX3D_CLK 3
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#define GPU_CC_CX_GFX3D_SLV_CLK 4
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+
#define GPU_CC_CX_GMU_CLK 5
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+
#define GPU_CC_CX_SNOC_DVM_CLK 6
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#define GPU_CC_CXO_AON_CLK 7
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+
#define GPU_CC_CXO_CLK 8
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#define GPU_CC_GMU_CLK_SRC 9
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#define GPU_CC_GX_CXO_CLK 10
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#define GPU_CC_GX_GFX3D_CLK 11
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#define GPU_CC_GX_GFX3D_CLK_SRC 12
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#define GPU_CC_GX_GMU_CLK 13
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+
#define GPU_CC_SLEEP_CLK 14
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+
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+
/* GDSCs */
28
+
#define GPU_CX_GDSC 0
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#define GPU_GX_GDSC 1
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+
31
+
/* Resets */
32
+
#define GPU_GX_BCR 0
33
+
#define GPU_ACD_BCR 1
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+
#define GPU_GX_ACD_MISC_BCR 2
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+
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+
#endif