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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
staging: fbtft: Use standard MIPI DCS command defines for st7735r
This patch makes use of the standard MIPI Display Command Set to remove
some of the magic constants found in source code.
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Priit Laes
and committed by
Greg Kroah-Hartman
79f5da7d
3d6924dd
+20
-22
+20
-22
drivers/staging/fbtft/fb_st7735r.c
+20
-22
drivers/staging/fbtft/fb_st7735r.c
···
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <video/mipi_display.h>
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#include "fbtft.h"
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···
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"0F 1B 0F 17 33 2C 29 2E 30 30 39 3F 00 07 03 10"
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static int default_init_sequence[] = {
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-
/* SWRESET - Software reset */
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-1, 0x01,
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-1, MIPI_DCS_SOFT_RESET,
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-2, 150, /* delay */
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-
/* SLPOUT - Sleep out & booster on */
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-1, 0x11,
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-1, MIPI_DCS_EXIT_SLEEP_MODE,
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-2, 500, /* delay */
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/* FRMCTR1 - frame rate control: normal mode
···
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/* VMCTR1 - Power Control */
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-1, 0xC5, 0x0E,
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-
/* INVOFF - Display inversion off */
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-1, 0x20,
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-1, MIPI_DCS_EXIT_INVERT_MODE,
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-
/* COLMOD - Interface pixel format */
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-1, 0x3A, 0x05,
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-1, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT,
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-
/* DISPON - Display On */
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-1, 0x29,
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-1, MIPI_DCS_SET_DISPLAY_ON,
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-2, 100, /* delay */
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/* NORON - Partial off (Normal) */
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-1, 0x13,
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-1, MIPI_DCS_ENTER_NORMAL_MODE,
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-2, 10, /* delay */
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/* end marker */
···
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static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
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{
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/* Column address */
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write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
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write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
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xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
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/* Row address */
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write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
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write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
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ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
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/* Memory write */
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write_reg(par, 0x2C);
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write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
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}
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#define MY BIT(7)
···
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RGB-BGR ORDER color filter panel: 0=RGB, 1=BGR */
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switch (par->info->var.rotate) {
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case 0:
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write_reg(par, 0x36, MX | MY | (par->bgr << 3));
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write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
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MX | MY | (par->bgr << 3));
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break;
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case 270:
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write_reg(par, 0x36, MY | MV | (par->bgr << 3));
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write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
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MY | MV | (par->bgr << 3));
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break;
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case 180:
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write_reg(par, 0x36, par->bgr << 3);
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write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
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par->bgr << 3);
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break;
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case 90:
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write_reg(par, 0x36, MX | MV | (par->bgr << 3));
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write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
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MX | MV | (par->bgr << 3));
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break;
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}
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