Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

staging: fbtft: Use standard MIPI DCS command defines for s6d02a1

This patch makes use of the standard MIPI Display Command Set to remove
some of the magic constants found in source code.

Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Priit Laes and committed by
Greg Kroah-Hartman
3d6924dd 49475ed0

+23 -19
+23 -19
drivers/staging/fbtft/fb_s6d02a1.c
··· 18 18 #include <linux/module.h> 19 19 #include <linux/kernel.h> 20 20 #include <linux/init.h> 21 + #include <video/mipi_display.h> 21 22 22 23 #include "fbtft.h" 23 24 ··· 51 50 52 51 -1, 0xf3, 0x00, 0x00, 53 52 54 - -1, 0x11, 53 + -1, MIPI_DCS_EXIT_SLEEP_MODE, 55 54 -2, 50, 56 55 57 56 -1, 0xf3, 0x00, 0x01, ··· 80 79 81 80 /* initializing sequence */ 82 81 83 - -1, 0x36, 0x08, 82 + -1, MIPI_DCS_SET_ADDRESS_MODE, 0x08, 84 83 85 - -1, 0x35, 0x00, 84 + -1, MIPI_DCS_SET_TEAR_ON, 0x00, 86 85 87 - -1, 0x3a, 0x05, 86 + -1, MIPI_DCS_SET_PIXEL_FORMAT, 0x05, 88 87 89 - /* gamma setting sequence */ 90 - -1, 0x26, 0x01, /* preset gamma curves, possible values 0x01, 0x02, 0x04, 0x08 */ 88 + /* gamma setting - possible values 0x01, 0x02, 0x04, 0x08 */ 89 + -1, MIPI_DCS_SET_GAMMA_CURVE, 0x01, 91 90 92 91 -2, 150, 93 - -1, 0x29, 94 - -1, 0x2c, 92 + -1, MIPI_DCS_SET_DISPLAY_ON, 93 + -1, MIPI_DCS_WRITE_MEMORY_START, 95 94 /* end marker */ 96 95 -3 97 96 ··· 99 98 100 99 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) 101 100 { 102 - /* Column address */ 103 - write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); 101 + write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS, 102 + xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); 104 103 105 - /* Row address */ 106 - write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); 104 + write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, 105 + ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); 107 106 108 - /* Memory write */ 109 - write_reg(par, 0x2C); 107 + write_reg(par, MIPI_DCS_WRITE_MEMORY_START); 110 108 } 111 109 112 110 #define MY BIT(7) ··· 113 113 #define MV BIT(5) 114 114 static int set_var(struct fbtft_par *par) 115 115 { 116 - /* MADCTL - Memory data access control 116 + /* Memory data access control (0x36h) 117 117 RGB/BGR: 118 118 1. Mode selection pin SRGB 119 119 RGB H/W pin for color filter setting: 0=RGB, 1=BGR ··· 121 121 RGB-BGR ORDER color filter panel: 0=RGB, 1=BGR */ 122 122 switch (par->info->var.rotate) { 123 123 case 0: 124 - write_reg(par, 0x36, MX | MY | (par->bgr << 3)); 124 + write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 125 + MX | MY | (par->bgr << 3)); 125 126 break; 126 127 case 270: 127 - write_reg(par, 0x36, MY | MV | (par->bgr << 3)); 128 + write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 129 + MY | MV | (par->bgr << 3)); 128 130 break; 129 131 case 180: 130 - write_reg(par, 0x36, par->bgr << 3); 132 + write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 133 + par->bgr << 3); 131 134 break; 132 135 case 90: 133 - write_reg(par, 0x36, MX | MV | (par->bgr << 3)); 136 + write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 137 + MX | MV | (par->bgr << 3)); 134 138 break; 135 139 } 136 140