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Documentation/gpu: Add an intro about MES
MES is an important firmware that lacks some essential documentation.
This commit introduces an overview of it and how it works.
Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Rodrigo Siqueira
and committed by
Alex Deucher
74f0ff36
e7aaa5fb
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Documentation/gpu/amdgpu/driver-core.rst
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Documentation/gpu/amdgpu/driver-core.rst
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Documentation/gpu/amdgpu/gc/index.rst
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Documentation/gpu/amdgpu/gc/index.rst
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GFX/compute engine.
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MES (MicroEngine Scheduler)
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This is the engine for managing queues.
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This is the engine for managing queues. For more details check
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:ref:`MicroEngine Scheduler (MES) <amdgpu-mes>`.
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RLC (RunList Controller)
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This is another microcontroller in the GFX/Compute engine. It handles
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power management related functionality within the GFX/Compute engine.
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The name is a vestige of old hardware where it was originally added
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and doesn't really have much relation to what the engine does now.
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.. toctree::
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mes.rst
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Documentation/gpu/amdgpu/gc/mes.rst
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Documentation/gpu/amdgpu/gc/mes.rst
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.. _amdgpu-mes:
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=============================
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MicroEngine Scheduler (MES)
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=============================
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.. note::
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Queue and ring buffer are used as a synonymous.
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.. note::
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This section assumes that you are familiar with the concept of Pipes, Queues, and GC.
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If not, check :ref:`GFX, Compute, and SDMA Overall Behavior<pipes-and-queues-description>`
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and :ref:`drm/amdgpu - Graphics and Compute (GC) <amdgpu-gc>`.
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Every GFX has a pipe component with one or more hardware queues. Pipes can
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switch between queues depending on certain conditions, and one of the
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components that can request a queue switch to a pipe is the MicroEngine
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Scheduler (MES). Whenever the driver is initialized, it creates one MQD per
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hardware queue, and then the MQDs are handed to the MES firmware for mapping
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to:
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1. Kernel Queues (legacy): This queue is statically mapped to HQDs and never
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preempted. Even though this is a legacy feature, it is the current default, and
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most existing hardware supports it. When an application submits work to the
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kernel driver, it submits all of the application command buffers to the kernel
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queues. The CS IOCTL takes the command buffer from the applications and
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schedules them on the kernel queue.
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2. User Queues: These queues are dynamically mapped to the HQDs. Regarding the
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utilization of User Queues, the userspace application will create its user
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queues and submit work directly to its user queues with no need to IOCTL for
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each submission and no need to share a single kernel queue.
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In terms of User Queues, MES can dynamically map them to the HQD. If there are
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more MQDs than HQDs, the MES firmware will preempt other user queues to make
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sure each queues get a time slice; in other words, MES is a microcontroller
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that handles the mapping and unmapping of MQDs into HQDs, as well as the
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priorities and oversubscription of MQDs.