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Documentation/gpu: Create a GC entry in the amdgpu documentation
GC is a large block that plays a vital role for amdgpu; for this reason,
this commit creates one specific page for GC and adds extra information
about the CP component.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Rodrigo Siqueira
and committed by
Alex Deucher
e7aaa5fb
4ede6d20
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Documentation/gpu/amdgpu/driver-core.rst
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Documentation/gpu/amdgpu/driver-core.rst
···
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This is the graphics and compute engine, i.e., the block that
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encompasses the 3D pipeline and and shader blocks. This is by far the
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largest block on the GPU. The 3D pipeline has tons of sub-blocks. In
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addition to that, it also contains the CP microcontrollers (ME, PFP,
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CE, MEC) and the RLC microcontroller. It's exposed to userspace for
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user mode drivers (OpenGL, Vulkan, OpenCL, etc.)
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addition to that, it also contains the CP microcontrollers (ME, PFP, CE,
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MEC) and the RLC microcontroller. It's exposed to userspace for user mode
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drivers (OpenGL, Vulkan, OpenCL, etc.). More details in :ref:`Graphics (GFX)
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and Compute <amdgpu-gc>`.
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VCN (Video Core Next)
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This is the multi-media engine. It handles video and image encode and
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decode. It's exposed to userspace for user mode drivers (VA-API,
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OpenMAX, etc.)
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Graphics and Compute Microcontrollers
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-------------------------------------
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CP (Command Processor)
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The name for the hardware block that encompasses the front end of the
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GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers
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(PFP, ME, CE, MEC). The firmware that runs on these microcontrollers
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provides the driver interface to interact with the GFX/Compute engine.
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MEC (MicroEngine Compute)
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This is the microcontroller that controls the compute queues on the
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GFX/compute engine.
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MES (MicroEngine Scheduler)
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This is a new engine for managing queues. This is currently unused.
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RLC (RunList Controller)
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This is another microcontroller in the GFX/Compute engine. It handles
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power management related functionality within the GFX/Compute engine.
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The name is a vestige of old hardware where it was originally added
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and doesn't really have much relation to what the engine does now.
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GFX, Compute, and SDMA Overall Behavior
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=======================================
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Documentation/gpu/amdgpu/gc/index.rst
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Documentation/gpu/amdgpu/gc/index.rst
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.. _amdgpu-gc:
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========================================
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drm/amdgpu - Graphics and Compute (GC)
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========================================
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The relationship between the CPU and GPU can be described as the
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producer-consumer problem, where the CPU fills out a buffer with operations
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(producer) to be executed by the GPU (consumer). The requested operations in
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the buffer are called Command Packets, which can be summarized as a compressed
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way of transmitting command information to the graphics controller.
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The component that acts as the front end between the CPU and the GPU is called
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the Command Processor (CP). This component is responsible for providing greater
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flexibility to the GC since CP makes it possible to program various aspects of
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the GPU pipeline. CP also coordinates the communication between the CPU and GPU
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via a mechanism named **Ring Buffers**, where the CPU appends information to
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the buffer while the GPU removes operations. It is relevant to highlight that a
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CPU can add a pointer to the Ring Buffer that points to another region of
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memory outside the Ring Buffer, and CP can handle it; this mechanism is called
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**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and
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writes the operations to the correct hardware blocks.
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Graphics (GFX) and Compute Microcontrollers
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-------------------------------------------
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GC is a large block, and as a result, it has multiple firmware associated with
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it. Some of them are:
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CP (Command Processor)
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The name for the hardware block that encompasses the front end of the
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GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers
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(PFP, ME, CE, MEC). The firmware that runs on these microcontrollers
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provides the driver interface to interact with the GFX/Compute engine.
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MEC (MicroEngine Compute)
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This is the microcontroller that controls the compute queues on the
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GFX/compute engine.
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MES (MicroEngine Scheduler)
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This is the engine for managing queues.
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RLC (RunList Controller)
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This is another microcontroller in the GFX/Compute engine. It handles
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power management related functionality within the GFX/Compute engine.
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The name is a vestige of old hardware where it was originally added
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and doesn't really have much relation to what the engine does now.